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Tom Rini53633a82024-02-29 12:33:36 -05001BCM2836 per-CPU interrupt controller
2
3The BCM2836 has a per-cpu interrupt controller for the timer, PMU
4events, and SMP IPIs. One of the CPUs may receive interrupts for the
5peripheral (GPU) events, which chain to the BCM2835-style interrupt
6controller.
7
8Required properties:
9
10- compatible: Should be "brcm,bcm2836-l1-intc"
11- reg: Specifies base physical address and size of the
12 registers
13- interrupt-controller: Identifies the node as an interrupt controller
14- #interrupt-cells: Specifies the number of cells needed to encode an
15 interrupt source. The value shall be 2
16
17Please refer to interrupts.txt in this directory for details of the common
18Interrupt Controllers bindings used by client devices.
19
20The interrupt sources are as follows:
21
220: CNTPSIRQ
231: CNTPNSIRQ
242: CNTHPIRQ
253: CNTVIRQ
268: GPU_FAST
279: PMU_FAST
28
29Example:
30
31local_intc: local_intc {
32 compatible = "brcm,bcm2836-l1-intc";
33 reg = <0x40000000 0x100>;
34 interrupt-controller;
35 #interrupt-cells = <2>;
36 interrupt-parent = <&local_intc>;
37};