blob: bb93baa888794b83d1613cecca79a383b528914a [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ZynqMP Mode Pin GPIO controller
8
9description:
10 PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
11 GPIO controller with configurable from numbers of pins (from 0 to 3 per
12 PS_MODE). Every pin can be configured as input/output.
13
14maintainers:
Tom Rini93743d22024-04-01 09:08:13 -040015 - Mubin Sayyed <mubin.sayyed@amd.com>
16 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Tom Rini53633a82024-02-29 12:33:36 -050017
18properties:
19 compatible:
20 const: xlnx,zynqmp-gpio-modepin
21
22 gpio-controller: true
23
24 "#gpio-cells":
25 const: 2
26
Tom Rini93743d22024-04-01 09:08:13 -040027 label: true
28
Tom Rini53633a82024-02-29 12:33:36 -050029required:
30 - compatible
31 - gpio-controller
32 - "#gpio-cells"
33
34additionalProperties: false
35
36examples:
37 - |
38 zynqmp-firmware {
39 gpio {
40 compatible = "xlnx,zynqmp-gpio-modepin";
41 gpio-controller;
42 #gpio-cells = <2>;
Tom Rini93743d22024-04-01 09:08:13 -040043 label = "modepin";
Tom Rini53633a82024-02-29 12:33:36 -050044 };
45 };
46
47...