| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Generic MMIO GPIO |
| 8 | |
| 9 | maintainers: |
| 10 | - Linus Walleij <linus.walleij@linaro.org> |
| 11 | - Bartosz Golaszewski <brgl@bgdev.pl> |
| 12 | |
| 13 | description: |
| 14 | Some simple GPIO controllers may consist of a single data register or a pair |
| 15 | of set/clear-bit registers. Such controllers are common for glue logic in |
| 16 | FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped |
| 17 | NAND-style parallel busses. |
| 18 | |
| 19 | properties: |
| 20 | compatible: |
| 21 | enum: |
| 22 | - brcm,bcm6345-gpio |
| 23 | - ni,169445-nand-gpio |
| 24 | - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller |
| 25 | |
| 26 | big-endian: true |
| 27 | |
| 28 | '#gpio-cells': |
| 29 | const: 2 |
| 30 | |
| 31 | gpio-controller: true |
| 32 | |
| 33 | little-endian: true |
| 34 | |
| 35 | reg: |
| 36 | minItems: 1 |
| 37 | description: |
| 38 | A list of registers in the controller. The width of each register is |
| 39 | determined by its size. All registers must have the same width. The number |
| 40 | of GPIOs is set by the width, with bit 0 corresponding to GPIO 0. |
| 41 | items: |
| 42 | - description: |
| 43 | Register to READ the value of the GPIO lines. If GPIO line is high, |
| 44 | the bit will be set. If the GPIO line is low, the bit will be cleared. |
| 45 | This register may also be used to drive GPIOs if the SET register is |
| 46 | omitted. |
| 47 | - description: |
| 48 | Register to SET the value of the GPIO lines. Setting a bit in this |
| 49 | register will drive the GPIO line high. |
| 50 | - description: |
| 51 | Register to CLEAR the value of the GPIO lines. Setting a bit in this |
| 52 | register will drive the GPIO line low. If this register is omitted, |
| 53 | the SET register will be used to clear the GPIO lines as well, by |
| 54 | actively writing the line with 0. |
| 55 | - description: |
| 56 | Register to set the line as OUTPUT. Setting a bit in this register |
| 57 | will turn that line into an output line. Conversely, clearing a bit |
| 58 | will turn that line into an input. |
| 59 | - description: |
| 60 | Register to set this line as INPUT. Setting a bit in this register |
| 61 | will turn that line into an input line. Conversely, clearing a bit |
| 62 | will turn that line into an output. |
| 63 | |
| 64 | reg-names: |
| 65 | minItems: 1 |
| 66 | maxItems: 5 |
| 67 | items: |
| 68 | enum: |
| 69 | - dat |
| 70 | - set |
| 71 | - clr |
| 72 | - dirout |
| 73 | - dirin |
| 74 | |
| 75 | native-endian: true |
| 76 | |
| 77 | no-output: |
| 78 | $ref: /schemas/types.yaml#/definitions/flag |
| 79 | description: |
| 80 | If this property is present, the controller cannot drive the GPIO lines. |
| 81 | |
| 82 | required: |
| 83 | - compatible |
| 84 | - reg |
| 85 | - reg-names |
| 86 | - '#gpio-cells' |
| 87 | - gpio-controller |
| 88 | |
| 89 | additionalProperties: false |
| 90 | |
| 91 | examples: |
| 92 | - | |
| 93 | gpio@1f300010 { |
| 94 | compatible = "ni,169445-nand-gpio"; |
| 95 | reg = <0x1f300010 0x4>; |
| 96 | reg-names = "dat"; |
| 97 | gpio-controller; |
| 98 | #gpio-cells = <2>; |
| 99 | }; |
| 100 | |
| 101 | gpio@e0100000 { |
| 102 | compatible = "wd,mbl-gpio"; |
| 103 | reg-names = "dat"; |
| 104 | reg = <0xe0100000 0x1>; |
| 105 | #gpio-cells = <2>; |
| 106 | gpio-controller; |
| 107 | no-output; |
| 108 | }; |
| 109 | |
| 110 | gpio@fffe0406 { |
| 111 | compatible = "brcm,bcm6345-gpio"; |
| 112 | reg-names = "dirout", "dat"; |
| 113 | reg = <0xfffe0406 2>, <0xfffe040a 2>; |
| 114 | native-endian; |
| 115 | gpio-controller; |
| 116 | #gpio-cells = <2>; |
| 117 | }; |