dts/upstream/Bindings/display/snps,arcpgu.txt

ARC PGU

This is a display controller found on several development boards produced
by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
framebuffer and sends it to a single digital encoder (usually HDMI).

Required properties:
  - compatible: "snps,arcpgu"
  - reg: Physical base address and length of the controller's registers.
  - clocks: A list of phandle + clock-specifier pairs, one for each
    entry in 'clock-names'.
  - clock-names: A list of clock names. For ARC PGU it should contain:
      - "pxlclk" for the clock feeding the output PLL of the controller.

Required sub-nodes:
  - port: The PGU connection to an encoder chip.

Example:

/ {
	...

	pgu@XXXXXXXX {
		compatible = "snps,arcpgu";
		reg = <0xXXXXXXXX 0x400>;
		clocks = <&clock_node>;
		clock-names = "pxlclk";

		port {
			pgu_output: endpoint {
				remote-endpoint = <&hdmi_enc_input>;
			};
		};
	};
};