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git01.mediatek.com / filogic / uboot / df41fc634d9e2e7899dc1023a7390708e6d8b886 / . / dts / upstream / Bindings / crypto / fsl,sec-v4.0.yaml
blob: 0a9ed2848b7c632bb34929e680767ab64180762e [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: GPL-2.0
2# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Freescale SEC 4
9
10maintainers:
11 - '"Horia Geantă" <horia.geanta@nxp.com>'
12 - Pankaj Gupta <pankaj.gupta@nxp.com>
13 - Gaurav Jain <gaurav.jain@nxp.com>
14
15description: |
16 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
17 Accelerator and Assurance Module (CAAM).
18
19 SEC 4 h/w can process requests from 2 types of sources.
20 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
21 2. Job Rings (HW interface between cores & SEC 4 registers).
22
23 High Speed Data Path Configuration:
24
25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
26 such as the P4080. The number of simultaneous dequeues the QI can make is
27 equal to the number of Descriptor Controller (DECO) engines in a particular
28 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
29 dequeue from 5 subportals simultaneously.
30
31 Job Ring Data Path Configuration:
32
33 Each JR is located on a separate 4k page, they may (or may not) be made visible
34 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
35 up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
36
37properties:
38 compatible:
39 oneOf:
40 - items:
41 - const: fsl,sec-v5.4
42 - const: fsl,sec-v5.0
43 - const: fsl,sec-v4.0
44 - items:
45 - enum:
46 - fsl,imx6ul-caam
47 - fsl,sec-v5.0
48 - const: fsl,sec-v4.0
49 - const: fsl,sec-v4.0
50
51 reg:
52 maxItems: 1
53
54 ranges:
55 maxItems: 1
56
57 '#address-cells':
58 enum: [1, 2]
59
60 '#size-cells':
61 enum: [1, 2]
62
63 clocks:
64 minItems: 1
65 maxItems: 4
66
67 clock-names:
68 minItems: 1
69 maxItems: 4
70 items:
71 enum: [mem, aclk, ipg, emi_slow]
72
73 dma-coherent: true
74
75 interrupts:
76 maxItems: 1
77
78 fsl,sec-era:
79 description: Defines the 'ERA' of the SEC device.
80 $ref: /schemas/types.yaml#/definitions/uint32
81
82patternProperties:
83 '^jr@[0-9a-f]+$':
84 type: object
85 additionalProperties: false
86 description:
87 Job Ring (JR) Node. Defines data processing interface to SEC 4 across the
88 peripheral bus for purposes of processing cryptographic descriptors. The
89 specified address range can be made visible to one (or more) cores. The
90 interrupt defined for this node is controlled within the address range of
91 this node.
92
93 properties:
94 compatible:
95 oneOf:
96 - items:
97 - const: fsl,sec-v5.4-job-ring
98 - const: fsl,sec-v5.0-job-ring
99 - const: fsl,sec-v4.0-job-ring
100 - items:
101 - const: fsl,sec-v5.0-job-ring
102 - const: fsl,sec-v4.0-job-ring
103 - const: fsl,sec-v4.0-job-ring
104
105 reg:
106 maxItems: 1
107
108 interrupts:
109 maxItems: 1
110
111 fsl,liodn:
112 description:
113 Specifies the LIODN to be used in conjunction with the ppid-to-liodn
114 table that specifies the PPID to LIODN mapping. Needed if the PAMU is
115 used. Value is a 12 bit value where value is a LIODN ID for this JR.
116 This property is normally set by boot firmware.
117 $ref: /schemas/types.yaml#/definitions/uint32
118 maximum: 0xfff
119
120 '^rtic@[0-9a-f]+$':
121 type: object
122 additionalProperties: false
123 description:
124 Run Time Integrity Check (RTIC) Node. Defines a register space that
125 contains up to 5 sets of addresses and their lengths (sizes) that will be
126 checked at run time. After an initial hash result is calculated, these
127 addresses are checked by HW to monitor any change. If any memory is
128 modified, a Security Violation is triggered (see SNVS definition).
129
130 properties:
131 compatible:
132 oneOf:
133 - items:
134 - const: fsl,sec-v5.4-rtic
135 - const: fsl,sec-v5.0-rtic
136 - const: fsl,sec-v4.0-rtic
137 - const: fsl,sec-v4.0-rtic
138
139 reg:
140 maxItems: 1
141
142 ranges:
143 maxItems: 1
144
145 interrupts:
146 maxItems: 1
147
148 '#address-cells':
149 const: 1
150
151 '#size-cells':
152 const: 1
153
154 patternProperties:
155 '^rtic-[a-z]@[0-9a-f]+$':
156 type: object
157 additionalProperties: false
158 description:
159 Run Time Integrity Check (RTIC) Memory Node defines individual RTIC
160 memory regions that are used to perform run-time integrity check of
161 memory areas that should not modified. The node defines a register
162 that contains the memory address & length (combined) and a second
163 register that contains the hash result in big endian format.
164
165 properties:
166 compatible:
167 oneOf:
168 - items:
169 - const: fsl,sec-v5.4-rtic-memory
170 - const: fsl,sec-v5.0-rtic-memory
171 - const: fsl,sec-v4.0-rtic-memory
172 - const: fsl,sec-v4.0-rtic-memory
173
174 reg:
175 items:
176 - description: RTIC memory address
177 - description: RTIC hash result
178
179 fsl,liodn:
180 description:
181 Specifies the LIODN to be used in conjunction with the
182 ppid-to-liodn table that specifies the PPID to LIODN mapping.
183 Needed if the PAMU is used. Value is a 12 bit value where value
184 is a LIODN ID for this JR. This property is normally set by boot
185 firmware.
186 $ref: /schemas/types.yaml#/definitions/uint32
187 maximum: 0xfff
188
189 fsl,rtic-region:
190 description:
191 Specifies the HW address (36 bit address) for this region
192 followed by the length of the HW partition to be checked;
193 the address is represented as a 64 bit quantity followed
194 by a 32 bit length.
195 $ref: /schemas/types.yaml#/definitions/uint32-array
196
197required:
198 - compatible
199 - reg
200 - ranges
201
202additionalProperties: false
203
204examples:
205 - |
206 crypto@300000 {
207 compatible = "fsl,sec-v4.0";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 reg = <0x300000 0x10000>;
211 ranges = <0 0x300000 0x10000>;
212 interrupts = <92 2>;
213
214 jr@1000 {
215 compatible = "fsl,sec-v4.0-job-ring";
216 reg = <0x1000 0x1000>;
217 interrupts = <88 2>;
218 };
219
220 jr@2000 {
221 compatible = "fsl,sec-v4.0-job-ring";
222 reg = <0x2000 0x1000>;
223 interrupts = <89 2>;
224 };
225
226 jr@3000 {
227 compatible = "fsl,sec-v4.0-job-ring";
228 reg = <0x3000 0x1000>;
229 interrupts = <90 2>;
230 };
231
232 jr@4000 {
233 compatible = "fsl,sec-v4.0-job-ring";
234 reg = <0x4000 0x1000>;
235 interrupts = <91 2>;
236 };
237
238 rtic@6000 {
239 compatible = "fsl,sec-v4.0-rtic";
240 #address-cells = <1>;
241 #size-cells = <1>;
242 reg = <0x6000 0x100>;
243 ranges = <0x0 0x6100 0xe00>;
244
245 rtic-a@0 {
246 compatible = "fsl,sec-v4.0-rtic-memory";
247 reg = <0x00 0x20>, <0x100 0x80>;
248 };
249
250 rtic-b@20 {
251 compatible = "fsl,sec-v4.0-rtic-memory";
252 reg = <0x20 0x20>, <0x200 0x80>;
253 };
254
255 rtic-c@40 {
256 compatible = "fsl,sec-v4.0-rtic-memory";
257 reg = <0x40 0x20>, <0x300 0x80>;
258 };
259
260 rtic-d@60 {
261 compatible = "fsl,sec-v4.0-rtic-memory";
262 reg = <0x60 0x20>, <0x500 0x80>;
263 };
264 };
265 };
266...