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git01.mediatek.com / filogic / uboot / df41fc634d9e2e7899dc1023a7390708e6d8b886 / . / dts / upstream / Bindings / clock / samsung,exynos5433-clock.yaml
blob: 3f9326e09f79ef55af1178a7bdad64693a1b8202 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos5433 SoC clock controller
8
9maintainers:
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
14
15description: |
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
17 name::
18 - "oscclk" - PLL input clock from XXTI
19
20 All available clocks are defined as preprocessor macros in
21 include/dt-bindings/clock/exynos5433.h header.
22
23properties:
24 compatible:
25 enum:
26 # CMU_TOP which generates clocks for
27 # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
28 # clocks
29 - samsung,exynos5433-cmu-top
30 # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
31 - samsung,exynos5433-cmu-cpif
32 # CMU_MIF which generates clocks for DRAM Memory Controller domain
33 - samsung,exynos5433-cmu-mif
34 # CMU_PERIC which generates clocks for
35 # UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs
36 - samsung,exynos5433-cmu-peric
37 # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
38 - samsung,exynos5433-cmu-peris
39 # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
40 - samsung,exynos5433-cmu-fsys
41 - samsung,exynos5433-cmu-g2d
42 # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
43 - samsung,exynos5433-cmu-disp
44 - samsung,exynos5433-cmu-aud
45 - samsung,exynos5433-cmu-bus0
46 - samsung,exynos5433-cmu-bus1
47 - samsung,exynos5433-cmu-bus2
48 - samsung,exynos5433-cmu-g3d
49 - samsung,exynos5433-cmu-gscl
50 - samsung,exynos5433-cmu-apollo
51 # CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor,
52 # CoreSight and L2 cache controller
53 - samsung,exynos5433-cmu-atlas
54 # CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and
55 # JPEG IPs
56 - samsung,exynos5433-cmu-mscl
57 - samsung,exynos5433-cmu-mfc
58 - samsung,exynos5433-cmu-hevc
59 # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
60 - samsung,exynos5433-cmu-isp
61 # CMU_CAM0 which generates clocks for
62 # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
63 - samsung,exynos5433-cmu-cam0
64 # CMU_CAM1 which generates clocks for
65 # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
66 - samsung,exynos5433-cmu-cam1
67 # CMU_IMEM which generates clocks for SSS (Security SubSystem) and
68 # SlimSSS IPs
69 - samsung,exynos5433-cmu-imem
70
71 clocks:
72 minItems: 1
73 maxItems: 10
74
75 clock-names:
76 minItems: 1
77 maxItems: 10
78
79 "#clock-cells":
80 const: 1
81
82 power-domains:
83 maxItems: 1
84
85 reg:
86 maxItems: 1
87
88required:
89 - compatible
90 - "#clock-cells"
91 - reg
92
93allOf:
94 - if:
95 properties:
96 compatible:
97 contains:
98 const: samsung,exynos5433-cmu-top
99 then:
100 properties:
101 clocks:
102 minItems: 4
103 maxItems: 4
104 clock-names:
105 items:
106 - const: oscclk
107 - const: sclk_mphy_pll
108 - const: sclk_mfc_pll
109 - const: sclk_bus_pll
110 required:
111 - clock-names
112 - clocks
113
114 - if:
115 properties:
116 compatible:
117 contains:
118 const: samsung,exynos5433-cmu-cpif
119 then:
120 properties:
121 clocks:
122 minItems: 1
123 maxItems: 1
124 clock-names:
125 items:
126 - const: oscclk
127 required:
128 - clock-names
129 - clocks
130
131 - if:
132 properties:
133 compatible:
134 contains:
135 const: samsung,exynos5433-cmu-mif
136 then:
137 properties:
138 clocks:
139 minItems: 2
140 maxItems: 2
141 clock-names:
142 items:
143 - const: oscclk
144 - const: sclk_mphy_pll
145 required:
146 - clock-names
147 - clocks
148
149 - if:
150 properties:
151 compatible:
152 contains:
153 const: samsung,exynos5433-cmu-fsys
154 then:
155 properties:
156 clocks:
157 minItems: 10
158 maxItems: 10
159 clock-names:
160 items:
161 - const: oscclk
162 - const: sclk_ufs_mphy
163 - const: aclk_fsys_200
164 - const: sclk_pcie_100_fsys
165 - const: sclk_ufsunipro_fsys
166 - const: sclk_mmc2_fsys
167 - const: sclk_mmc1_fsys
168 - const: sclk_mmc0_fsys
169 - const: sclk_usbhost30_fsys
170 - const: sclk_usbdrd30_fsys
171 required:
172 - clock-names
173 - clocks
174
175 - if:
176 properties:
177 compatible:
178 contains:
179 const: samsung,exynos5433-cmu-g2d
180 then:
181 properties:
182 clocks:
183 minItems: 3
184 maxItems: 3
185 clock-names:
186 items:
187 - const: oscclk
188 - const: aclk_g2d_266
189 - const: aclk_g2d_400
190 required:
191 - clock-names
192 - clocks
193
194 - if:
195 properties:
196 compatible:
197 contains:
198 const: samsung,exynos5433-cmu-disp
199 then:
200 properties:
201 clocks:
202 minItems: 9
203 maxItems: 9
204 clock-names:
205 items:
206 - const: oscclk
207 - const: sclk_dsim1_disp
208 - const: sclk_dsim0_disp
209 - const: sclk_dsd_disp
210 - const: sclk_decon_tv_eclk_disp
211 - const: sclk_decon_vclk_disp
212 - const: sclk_decon_eclk_disp
213 - const: sclk_decon_tv_vclk_disp
214 - const: aclk_disp_333
215 required:
216 - clock-names
217 - clocks
218
219 - if:
220 properties:
221 compatible:
222 contains:
223 const: samsung,exynos5433-cmu-aud
224 then:
225 properties:
226 clocks:
227 minItems: 2
228 maxItems: 2
229 clock-names:
230 items:
231 - const: oscclk
232 - const: fout_aud_pll
233 required:
234 - clock-names
235 - clocks
236
237 - if:
238 properties:
239 compatible:
240 contains:
241 const: samsung,exynos5433-cmu-bus0
242 then:
243 properties:
244 clocks:
245 minItems: 1
246 maxItems: 1
247 clock-names:
248 items:
249 - const: aclk_bus0_400
250 required:
251 - clock-names
252 - clocks
253
254 - if:
255 properties:
256 compatible:
257 contains:
258 const: samsung,exynos5433-cmu-bus1
259 then:
260 properties:
261 clocks:
262 minItems: 1
263 maxItems: 1
264 clock-names:
265 items:
266 - const: aclk_bus1_400
267 required:
268 - clock-names
269 - clocks
270
271 - if:
272 properties:
273 compatible:
274 contains:
275 const: samsung,exynos5433-cmu-bus2
276 then:
277 properties:
278 clocks:
279 minItems: 2
280 maxItems: 2
281 clock-names:
282 items:
283 - const: oscclk
284 - const: aclk_bus2_400
285 required:
286 - clock-names
287 - clocks
288
289 - if:
290 properties:
291 compatible:
292 contains:
293 const: samsung,exynos5433-cmu-g3d
294 then:
295 properties:
296 clocks:
297 minItems: 2
298 maxItems: 2
299 clock-names:
300 items:
301 - const: oscclk
302 - const: aclk_g3d_400
303 required:
304 - clock-names
305 - clocks
306
307 - if:
308 properties:
309 compatible:
310 contains:
311 const: samsung,exynos5433-cmu-gscl
312 then:
313 properties:
314 clocks:
315 minItems: 3
316 maxItems: 3
317 clock-names:
318 items:
319 - const: oscclk
320 - const: aclk_gscl_111
321 - const: aclk_gscl_333
322 required:
323 - clock-names
324 - clocks
325
326 - if:
327 properties:
328 compatible:
329 contains:
330 const: samsung,exynos5433-cmu-apollo
331 then:
332 properties:
333 clocks:
334 minItems: 2
335 maxItems: 2
336 clock-names:
337 items:
338 - const: oscclk
339 - const: sclk_bus_pll_apollo
340 required:
341 - clock-names
342 - clocks
343
344 - if:
345 properties:
346 compatible:
347 contains:
348 const: samsung,exynos5433-cmu-atlas
349 then:
350 properties:
351 clocks:
352 minItems: 2
353 maxItems: 2
354 clock-names:
355 items:
356 - const: oscclk
357 - const: sclk_bus_pll_atlas
358 required:
359 - clock-names
360 - clocks
361
362 - if:
363 properties:
364 compatible:
365 contains:
366 const: samsung,exynos5433-cmu-mscl
367 then:
368 properties:
369 clocks:
370 minItems: 3
371 maxItems: 3
372 clock-names:
373 items:
374 - const: oscclk
375 - const: sclk_jpeg_mscl
376 - const: aclk_mscl_400
377 required:
378 - clock-names
379 - clocks
380
381 - if:
382 properties:
383 compatible:
384 contains:
385 const: samsung,exynos5433-cmu-mfc
386 then:
387 properties:
388 clocks:
389 minItems: 2
390 maxItems: 2
391 clock-names:
392 items:
393 - const: oscclk
394 - const: aclk_mfc_400
395 required:
396 - clock-names
397 - clocks
398
399 - if:
400 properties:
401 compatible:
402 contains:
403 const: samsung,exynos5433-cmu-hevc
404 then:
405 properties:
406 clocks:
407 minItems: 2
408 maxItems: 2
409 clock-names:
410 items:
411 - const: oscclk
412 - const: aclk_hevc_400
413 required:
414 - clock-names
415 - clocks
416
417 - if:
418 properties:
419 compatible:
420 contains:
421 const: samsung,exynos5433-cmu-isp
422 then:
423 properties:
424 clocks:
425 minItems: 3
426 maxItems: 3
427 clock-names:
428 items:
429 - const: oscclk
430 - const: aclk_isp_dis_400
431 - const: aclk_isp_400
432 required:
433 - clock-names
434 - clocks
435
436 - if:
437 properties:
438 compatible:
439 contains:
440 const: samsung,exynos5433-cmu-cam0
441 then:
442 properties:
443 clocks:
444 minItems: 4
445 maxItems: 4
446 clock-names:
447 items:
448 - const: oscclk
449 - const: aclk_cam0_333
450 - const: aclk_cam0_400
451 - const: aclk_cam0_552
452 required:
453 - clock-names
454 - clocks
455
456 - if:
457 properties:
458 compatible:
459 contains:
460 const: samsung,exynos5433-cmu-cam1
461 then:
462 properties:
463 clocks:
464 minItems: 7
465 maxItems: 7
466 clock-names:
467 items:
468 - const: oscclk
469 - const: sclk_isp_uart_cam1
470 - const: sclk_isp_spi1_cam1
471 - const: sclk_isp_spi0_cam1
472 - const: aclk_cam1_333
473 - const: aclk_cam1_400
474 - const: aclk_cam1_552
475 required:
476 - clock-names
477 - clocks
478
479 - if:
480 properties:
481 compatible:
482 contains:
483 const: samsung,exynos5433-cmu-imem
484 then:
485 properties:
486 clocks:
487 minItems: 4
488 maxItems: 4
489 clock-names:
490 items:
491 - const: oscclk
492 - const: aclk_imem_sssx_266
493 - const: aclk_imem_266
494 - const: aclk_imem_200
495 required:
496 - clock-names
497 - clocks
498
499additionalProperties: false
500
501examples:
502 - |
503 #include <dt-bindings/clock/exynos5433.h>
504 xxti: clock {
505 compatible = "fixed-clock";
506 clock-output-names = "oscclk";
507 #clock-cells = <0>;
508 clock-frequency = <24000000>;
509 };
510
511 clock-controller@10030000 {
512 compatible = "samsung,exynos5433-cmu-top";
513 reg = <0x10030000 0x1000>;
514 #clock-cells = <1>;
515
516 clock-names = "oscclk",
517 "sclk_mphy_pll",
518 "sclk_mfc_pll",
519 "sclk_bus_pll";
520 clocks = <&xxti>,
521 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
522 <&cmu_mif CLK_SCLK_MFC_PLL>,
523 <&cmu_mif CLK_SCLK_BUS_PLL>;
524 };