blob: 2d44ddc45aabb22e5a3166d1504e0a1e96037c1b [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on IPQ8074
8
9maintainers:
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
12
13description: |
14 Qualcomm global clock control module provides the clocks, resets and power
15 domains on IPQ8074.
16
17 See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h
18
19allOf:
20 - $ref: qcom,gcc.yaml#
21
22properties:
23 compatible:
24 const: qcom,gcc-ipq8074
25
26 clocks:
27 items:
28 - description: board XO clock
29 - description: sleep clock
Tom Rini93743d22024-04-01 09:08:13 -040030 - description: Gen3 QMP PCIe PHY PIPE clock
31 - description: Gen2 QMP PCIe PHY PIPE clock
Tom Rini53633a82024-02-29 12:33:36 -050032
33 clock-names:
34 items:
35 - const: xo
36 - const: sleep_clk
Tom Rini93743d22024-04-01 09:08:13 -040037 - const: pcie0_pipe
38 - const: pcie1_pipe
Tom Rini53633a82024-02-29 12:33:36 -050039
40required:
41 - compatible
42
43unevaluatedProperties: false
44
45examples:
46 - |
47 clock-controller@1800000 {
48 compatible = "qcom,gcc-ipq8074";
49 reg = <0x01800000 0x80000>;
50 #clock-cells = <1>;
51 #power-domain-cells = <1>;
52 #reset-cells = <1>;
53 };
54...