dts/upstream/Bindings/clock/mediatek,mt7621-sysc.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MT7621 Clock

maintainers:
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description: |
  The MT7621 has a PLL controller from where the cpu clock is provided
  as well as derived clocks for the bus and the peripherals. It also
  can gate SoC device clocks.

  Each clock is assigned an identifier and client nodes use this identifier
  to specify the clock which they consume.

  All these identifiers could be found in:
  [1]: <include/dt-bindings/clock/mt7621-clk.h>.

  The clocks are provided inside a system controller node.

  This node is also a reset provider for all the peripherals.

  Reset related bits are defined in:
  [2]: <include/dt-bindings/reset/mt7621-reset.h>.

properties:
  compatible:
    items:
      - const: mediatek,mt7621-sysc
      - const: syscon

  reg:
    maxItems: 1

  "#clock-cells":
    description:
      The first cell indicates the clock number, see [1] for available
      clocks.
    const: 1

  "#reset-cells":
    description:
      The first cell indicates the reset bit within the register, see
      [2] for available resets.
    const: 1

  ralink,memctl:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle of syscon used to control memory registers

  clock-output-names:
    maxItems: 8

required:
  - compatible
  - reg
  - '#clock-cells'
  - ralink,memctl

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt7621-clk.h>

    sysc: sysc@0 {
      compatible = "mediatek,mt7621-sysc", "syscon";
      reg = <0x0 0x100>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      ralink,memctl = <&memc>;
      clock-output-names = "xtal", "cpu", "bus",
                           "50m", "125m", "150m",
                           "250m", "270m";
    };