blob: 9e7c725093aa1bea64dc48910a68015adf8731d3 [file] [log] [blame]
Tom Rini6bb92fc2024-05-20 09:54:58 -06001# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,mt2701-hifsys.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek HIFSYS clock and reset controller
8
9description:
10 The MediaTek HIFSYS controller provides various clocks and reset outputs to
11 the system.
12
13maintainers:
14 - Matthias Brugger <matthias.bgg@gmail.com>
15
16properties:
17 compatible:
18 oneOf:
19 - enum:
20 - mediatek,mt2701-hifsys
21 - mediatek,mt7622-hifsys
22 - items:
23 - enum:
24 - mediatek,mt7623-hifsys
25 - const: mediatek,mt2701-hifsys
26
27 reg:
28 maxItems: 1
29
30 "#clock-cells":
31 const: 1
32 description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
33
34 "#reset-cells":
35 const: 1
36
37required:
38 - reg
39 - "#clock-cells"
40
41additionalProperties: false
42
43examples:
44 - |
45 clock-controller@1a000000 {
46 compatible = "mediatek,mt2701-hifsys";
47 reg = <0x1a000000 0x1000>;
48 #clock-cells = <1>;
49 #reset-cells = <1>;
50 };