dts/upstream/Bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 DRAM PLL

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

deprecated: true

properties:
  "#clock-cells":
    const: 1
    description: >
      The first output is the DRAM clock output, the second is meant
      for peripherals on the SoC.

  compatible:
    const: allwinner,sun4i-a10-pll5-clk

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-output-names:
    maxItems: 2

required:
  - "#clock-cells"
  - compatible
  - reg
  - clocks
  - clock-output-names

additionalProperties: false

examples:
  - |
    clk@1c20020 {
        #clock-cells = <1>;
        compatible = "allwinner,sun4i-a10-pll5-clk";
        reg = <0x01c20020 0x4>;
        clocks = <&osc24M>;
        clock-output-names = "pll5_ddr", "pll5_other";
    };

...