David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2019 Rockchip Electronics Co., Ltd |
| 4 | */ |
| 5 | |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 6 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 7 | #include <log.h> |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 8 | #include <dm/pinctrl.h> |
| 9 | #include <regmap.h> |
| 10 | #include <syscon.h> |
| 11 | #include <fdtdec.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 12 | #include <linux/bitops.h> |
Simon Glass | 2dc9c34 | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 13 | #include <linux/libfdt.h> |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 14 | |
| 15 | #include "pinctrl-rockchip.h" |
| 16 | |
| 17 | #define MAX_ROCKCHIP_PINS_ENTRIES 30 |
| 18 | #define MAX_ROCKCHIP_GPIO_PER_BANK 32 |
| 19 | #define RK_FUNC_GPIO 0 |
| 20 | |
| 21 | static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) |
| 22 | { |
| 23 | struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); |
| 24 | struct rockchip_pin_ctrl *ctrl = priv->ctrl; |
| 25 | |
| 26 | if (bank >= ctrl->nr_banks) { |
| 27 | debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); |
| 28 | return -EINVAL; |
| 29 | } |
| 30 | |
| 31 | if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { |
| 32 | debug("pin conf pin %d >= %d\n", pin, |
| 33 | MAX_ROCKCHIP_GPIO_PER_BANK); |
| 34 | return -EINVAL; |
| 35 | } |
| 36 | |
| 37 | return 0; |
| 38 | } |
| 39 | |
David Wu | 3dd7d6c | 2019-04-16 21:50:55 +0800 | [diff] [blame] | 40 | void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, |
| 41 | int *reg, u8 *bit, int *mask) |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 42 | { |
| 43 | struct rockchip_pinctrl_priv *priv = bank->priv; |
| 44 | struct rockchip_pin_ctrl *ctrl = priv->ctrl; |
| 45 | struct rockchip_mux_recalced_data *data; |
| 46 | int i; |
| 47 | |
| 48 | for (i = 0; i < ctrl->niomux_recalced; i++) { |
| 49 | data = &ctrl->iomux_recalced[i]; |
| 50 | if (data->num == bank->bank_num && |
| 51 | data->pin == pin) |
| 52 | break; |
| 53 | } |
| 54 | |
| 55 | if (i >= ctrl->niomux_recalced) |
| 56 | return; |
| 57 | |
| 58 | *reg = data->reg; |
| 59 | *mask = data->mask; |
| 60 | *bit = data->bit; |
| 61 | } |
| 62 | |
Jagan Teki | 9e0e681 | 2022-12-14 23:20:56 +0530 | [diff] [blame] | 63 | static enum rockchip_pin_route_type |
| 64 | rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, |
| 65 | int mux, u32 *reg, u32 *value) |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 66 | { |
| 67 | struct rockchip_pinctrl_priv *priv = bank->priv; |
| 68 | struct rockchip_pin_ctrl *ctrl = priv->ctrl; |
| 69 | struct rockchip_mux_route_data *data; |
| 70 | int i; |
| 71 | |
| 72 | for (i = 0; i < ctrl->niomux_routes; i++) { |
| 73 | data = &ctrl->iomux_routes[i]; |
| 74 | if (data->bank_num == bank->bank_num && |
| 75 | data->pin == pin && data->func == mux) |
| 76 | break; |
| 77 | } |
| 78 | |
| 79 | if (i >= ctrl->niomux_routes) |
Jagan Teki | 9e0e681 | 2022-12-14 23:20:56 +0530 | [diff] [blame] | 80 | return ROUTE_TYPE_INVALID; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 81 | |
| 82 | *reg = data->route_offset; |
| 83 | *value = data->route_val; |
| 84 | |
Jagan Teki | 9e0e681 | 2022-12-14 23:20:56 +0530 | [diff] [blame] | 85 | return data->route_type; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 86 | } |
| 87 | |
David Wu | 3dd7d6c | 2019-04-16 21:50:55 +0800 | [diff] [blame] | 88 | int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 89 | { |
| 90 | int offset = 0; |
| 91 | |
| 92 | if (mux_type & IOMUX_WIDTH_4BIT) { |
| 93 | if ((pin % 8) >= 4) |
| 94 | offset = 0x4; |
| 95 | *bit = (pin % 4) * 4; |
| 96 | *mask = 0xf; |
| 97 | } else if (mux_type & IOMUX_WIDTH_3BIT) { |
| 98 | /* |
| 99 | * pin0 ~ pin4 are at first register, and |
| 100 | * pin5 ~ pin7 are at second register. |
| 101 | */ |
| 102 | if ((pin % 8) >= 5) |
| 103 | offset = 0x4; |
| 104 | *bit = (pin % 8 % 5) * 3; |
| 105 | *mask = 0x7; |
| 106 | } else { |
| 107 | *bit = (pin % 8) * 2; |
| 108 | *mask = 0x3; |
| 109 | } |
| 110 | |
| 111 | return offset; |
| 112 | } |
| 113 | |
| 114 | static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) |
| 115 | { |
| 116 | struct rockchip_pinctrl_priv *priv = bank->priv; |
| 117 | int iomux_num = (pin / 8); |
| 118 | struct regmap *regmap; |
| 119 | unsigned int val; |
| 120 | int reg, ret, mask, mux_type; |
| 121 | u8 bit; |
| 122 | |
| 123 | if (iomux_num > 3) |
| 124 | return -EINVAL; |
| 125 | |
| 126 | if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { |
| 127 | debug("pin %d is unrouted\n", pin); |
| 128 | return -EINVAL; |
| 129 | } |
| 130 | |
| 131 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) |
| 132 | return RK_FUNC_GPIO; |
| 133 | |
| 134 | regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
| 135 | ? priv->regmap_pmu : priv->regmap_base; |
| 136 | |
| 137 | /* get basic quadrupel of mux registers and the correct reg inside */ |
| 138 | mux_type = bank->iomux[iomux_num].type; |
| 139 | reg = bank->iomux[iomux_num].offset; |
| 140 | reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); |
| 141 | |
| 142 | if (bank->recalced_mask & BIT(pin)) |
| 143 | rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); |
| 144 | |
| 145 | ret = regmap_read(regmap, reg, &val); |
| 146 | if (ret) |
| 147 | return ret; |
| 148 | |
| 149 | return ((val >> bit) & mask); |
| 150 | } |
| 151 | |
| 152 | static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, |
| 153 | int index) |
| 154 | { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); |
| 155 | struct rockchip_pin_ctrl *ctrl = priv->ctrl; |
| 156 | |
| 157 | return rockchip_get_mux(&ctrl->pin_banks[banknum], index); |
| 158 | } |
| 159 | |
| 160 | static int rockchip_verify_mux(struct rockchip_pin_bank *bank, |
| 161 | int pin, int mux) |
| 162 | { |
| 163 | int iomux_num = (pin / 8); |
| 164 | |
| 165 | if (iomux_num > 3) |
| 166 | return -EINVAL; |
| 167 | |
| 168 | if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { |
| 169 | debug("pin %d is unrouted\n", pin); |
| 170 | return -EINVAL; |
| 171 | } |
| 172 | |
| 173 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { |
| 174 | if (mux != IOMUX_GPIO_ONLY) { |
| 175 | debug("pin %d only supports a gpio mux\n", pin); |
| 176 | return -ENOTSUPP; |
| 177 | } |
| 178 | } |
| 179 | |
| 180 | return 0; |
| 181 | } |
| 182 | |
| 183 | /* |
| 184 | * Set a new mux function for a pin. |
| 185 | * |
| 186 | * The register is divided into the upper and lower 16 bit. When changing |
| 187 | * a value, the previous register value is not read and changed. Instead |
| 188 | * it seems the changed bits are marked in the upper 16 bit, while the |
| 189 | * changed value gets set in the same offset in the lower 16 bit. |
| 190 | * All pin settings seem to be 2 bit wide in both the upper and lower |
| 191 | * parts. |
| 192 | * @bank: pin bank to change |
| 193 | * @pin: pin to change |
| 194 | * @mux: new mux function to set |
| 195 | */ |
| 196 | static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) |
| 197 | { |
| 198 | struct rockchip_pinctrl_priv *priv = bank->priv; |
David Wu | 3dd7d6c | 2019-04-16 21:50:55 +0800 | [diff] [blame] | 199 | struct rockchip_pin_ctrl *ctrl = priv->ctrl; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 200 | int iomux_num = (pin / 8); |
David Wu | 3dd7d6c | 2019-04-16 21:50:55 +0800 | [diff] [blame] | 201 | int ret; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 202 | |
| 203 | ret = rockchip_verify_mux(bank, pin, mux); |
| 204 | if (ret < 0) |
| 205 | return ret; |
| 206 | |
| 207 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) |
| 208 | return 0; |
| 209 | |
| 210 | debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); |
| 211 | |
David Wu | 3dd7d6c | 2019-04-16 21:50:55 +0800 | [diff] [blame] | 212 | if (!ctrl->set_mux) |
| 213 | return -ENOTSUPP; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 214 | |
David Wu | 3dd7d6c | 2019-04-16 21:50:55 +0800 | [diff] [blame] | 215 | ret = ctrl->set_mux(bank, pin, mux); |
Jagan Teki | 9e0e681 | 2022-12-14 23:20:56 +0530 | [diff] [blame] | 216 | if (ret) |
| 217 | return ret; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 218 | |
Jagan Teki | 9e0e681 | 2022-12-14 23:20:56 +0530 | [diff] [blame] | 219 | if (bank->route_mask & BIT(pin)) { |
| 220 | struct regmap *regmap; |
| 221 | u32 route_reg = 0, route_val = 0; |
| 222 | |
| 223 | ret = rockchip_get_mux_route(bank, pin, mux, |
| 224 | &route_reg, &route_val); |
| 225 | switch (ret) { |
| 226 | case ROUTE_TYPE_DEFAULT: |
| 227 | if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
| 228 | regmap = priv->regmap_pmu; |
| 229 | else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) |
| 230 | regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; |
| 231 | else |
| 232 | regmap = priv->regmap_base; |
| 233 | |
| 234 | regmap_write(regmap, route_reg, route_val); |
| 235 | break; |
| 236 | case ROUTE_TYPE_TOPGRF: |
| 237 | regmap_write(priv->regmap_base, route_reg, route_val); |
| 238 | break; |
| 239 | case ROUTE_TYPE_PMUGRF: |
| 240 | regmap_write(priv->regmap_pmu, route_reg, route_val); |
| 241 | break; |
| 242 | case ROUTE_TYPE_INVALID: |
| 243 | fallthrough; |
| 244 | default: |
| 245 | break; |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | return 0; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { |
| 253 | { 2, 4, 8, 12, -1, -1, -1, -1 }, |
| 254 | { 3, 6, 9, 12, -1, -1, -1, -1 }, |
| 255 | { 5, 10, 15, 20, -1, -1, -1, -1 }, |
| 256 | { 4, 6, 8, 10, 12, 14, 16, 18 }, |
| 257 | { 4, 7, 10, 13, 16, 19, 22, 26 } |
| 258 | }; |
| 259 | |
David Wu | 40a5548 | 2019-04-16 21:55:26 +0800 | [diff] [blame] | 260 | int rockchip_translate_drive_value(int type, int strength) |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 261 | { |
David Wu | 40a5548 | 2019-04-16 21:55:26 +0800 | [diff] [blame] | 262 | int i, ret; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 263 | |
| 264 | ret = -EINVAL; |
David Wu | 40a5548 | 2019-04-16 21:55:26 +0800 | [diff] [blame] | 265 | for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) { |
| 266 | if (rockchip_perpin_drv_list[type][i] == strength) { |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 267 | ret = i; |
| 268 | break; |
David Wu | 40a5548 | 2019-04-16 21:55:26 +0800 | [diff] [blame] | 269 | } else if (rockchip_perpin_drv_list[type][i] < 0) { |
| 270 | ret = rockchip_perpin_drv_list[type][i]; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 271 | break; |
| 272 | } |
| 273 | } |
| 274 | |
David Wu | 40a5548 | 2019-04-16 21:55:26 +0800 | [diff] [blame] | 275 | return ret; |
| 276 | } |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 277 | |
David Wu | 40a5548 | 2019-04-16 21:55:26 +0800 | [diff] [blame] | 278 | static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, |
| 279 | int pin_num, int strength) |
| 280 | { |
| 281 | struct rockchip_pinctrl_priv *priv = bank->priv; |
| 282 | struct rockchip_pin_ctrl *ctrl = priv->ctrl; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 283 | |
David Wu | 40a5548 | 2019-04-16 21:55:26 +0800 | [diff] [blame] | 284 | debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, |
| 285 | pin_num, strength); |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 286 | |
David Wu | 40a5548 | 2019-04-16 21:55:26 +0800 | [diff] [blame] | 287 | if (!ctrl->set_drive) |
| 288 | return -ENOTSUPP; |
Kever Yang | 56573c4 | 2019-05-07 09:36:32 +0800 | [diff] [blame] | 289 | |
David Wu | 40a5548 | 2019-04-16 21:55:26 +0800 | [diff] [blame] | 290 | return ctrl->set_drive(bank, pin_num, strength); |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | static int rockchip_pull_list[PULL_TYPE_MAX][4] = { |
| 294 | { |
| 295 | PIN_CONFIG_BIAS_DISABLE, |
| 296 | PIN_CONFIG_BIAS_PULL_UP, |
| 297 | PIN_CONFIG_BIAS_PULL_DOWN, |
| 298 | PIN_CONFIG_BIAS_BUS_HOLD |
| 299 | }, |
| 300 | { |
| 301 | PIN_CONFIG_BIAS_DISABLE, |
| 302 | PIN_CONFIG_BIAS_PULL_DOWN, |
| 303 | PIN_CONFIG_BIAS_DISABLE, |
| 304 | PIN_CONFIG_BIAS_PULL_UP |
| 305 | }, |
| 306 | }; |
| 307 | |
David Wu | 2972c45 | 2019-04-16 21:57:05 +0800 | [diff] [blame] | 308 | int rockchip_translate_pull_value(int type, int pull) |
| 309 | { |
| 310 | int i, ret; |
| 311 | |
| 312 | ret = -EINVAL; |
| 313 | for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]); |
| 314 | i++) { |
| 315 | if (rockchip_pull_list[type][i] == pull) { |
| 316 | ret = i; |
| 317 | break; |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | return ret; |
| 322 | } |
| 323 | |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 324 | static int rockchip_set_pull(struct rockchip_pin_bank *bank, |
| 325 | int pin_num, int pull) |
| 326 | { |
| 327 | struct rockchip_pinctrl_priv *priv = bank->priv; |
| 328 | struct rockchip_pin_ctrl *ctrl = priv->ctrl; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 329 | |
| 330 | debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, |
| 331 | pin_num, pull); |
| 332 | |
David Wu | 2972c45 | 2019-04-16 21:57:05 +0800 | [diff] [blame] | 333 | if (!ctrl->set_pull) |
| 334 | return -ENOTSUPP; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 335 | |
David Wu | 2972c45 | 2019-04-16 21:57:05 +0800 | [diff] [blame] | 336 | return ctrl->set_pull(bank, pin_num, pull); |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 337 | } |
| 338 | |
| 339 | static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, |
| 340 | int pin_num, int enable) |
| 341 | { |
| 342 | struct rockchip_pinctrl_priv *priv = bank->priv; |
| 343 | struct rockchip_pin_ctrl *ctrl = priv->ctrl; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 344 | |
| 345 | debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, |
| 346 | pin_num, enable); |
| 347 | |
David Wu | 7ae4ec9 | 2019-04-16 21:58:13 +0800 | [diff] [blame] | 348 | if (!ctrl->set_schmitt) |
| 349 | return -ENOTSUPP; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 350 | |
David Wu | 7ae4ec9 | 2019-04-16 21:58:13 +0800 | [diff] [blame] | 351 | return ctrl->set_schmitt(bank, pin_num, enable); |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 352 | } |
| 353 | |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 354 | /* set the pin config settings for a specified pin */ |
| 355 | static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, |
| 356 | u32 pin, u32 param, u32 arg) |
| 357 | { |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 358 | int rc; |
| 359 | |
| 360 | switch (param) { |
| 361 | case PIN_CONFIG_BIAS_DISABLE: |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 362 | case PIN_CONFIG_BIAS_PULL_UP: |
| 363 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 364 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: |
| 365 | case PIN_CONFIG_BIAS_BUS_HOLD: |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 366 | rc = rockchip_set_pull(bank, pin, param); |
| 367 | if (rc) |
| 368 | return rc; |
| 369 | break; |
| 370 | |
| 371 | case PIN_CONFIG_DRIVE_STRENGTH: |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 372 | rc = rockchip_set_drive_perpin(bank, pin, arg); |
| 373 | if (rc < 0) |
| 374 | return rc; |
| 375 | break; |
| 376 | |
| 377 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 378 | rc = rockchip_set_schmitt(bank, pin, arg); |
| 379 | if (rc < 0) |
| 380 | return rc; |
| 381 | break; |
| 382 | |
| 383 | default: |
| 384 | break; |
| 385 | } |
| 386 | |
| 387 | return 0; |
| 388 | } |
| 389 | |
| 390 | static const struct pinconf_param rockchip_conf_params[] = { |
| 391 | { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, |
| 392 | { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, |
| 393 | { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, |
| 394 | { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, |
David Wu | 1856451 | 2019-04-16 21:50:53 +0800 | [diff] [blame] | 395 | { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 396 | { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 397 | { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, |
| 398 | { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, |
| 399 | }; |
| 400 | |
| 401 | static int rockchip_pinconf_prop_name_to_param(const char *property, |
| 402 | u32 *default_value) |
| 403 | { |
| 404 | const struct pinconf_param *p, *end; |
| 405 | |
| 406 | p = rockchip_conf_params; |
| 407 | end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); |
| 408 | |
| 409 | /* See if this pctldev supports this parameter */ |
| 410 | for (; p < end; p++) { |
| 411 | if (!strcmp(property, p->property)) { |
| 412 | *default_value = p->default_value; |
| 413 | return p->param; |
| 414 | } |
| 415 | } |
| 416 | |
| 417 | *default_value = 0; |
| 418 | return -EPERM; |
| 419 | } |
| 420 | |
| 421 | static int rockchip_pinctrl_set_state(struct udevice *dev, |
| 422 | struct udevice *config) |
| 423 | { |
| 424 | struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); |
| 425 | struct rockchip_pin_ctrl *ctrl = priv->ctrl; |
| 426 | u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; |
| 427 | u32 bank, pin, mux, conf, arg, default_val; |
| 428 | int ret, count, i; |
| 429 | const char *prop_name; |
| 430 | const void *value; |
| 431 | int prop_len, param; |
| 432 | const u32 *data; |
| 433 | ofnode node; |
Jonas Karlman | 420b010 | 2023-06-08 10:59:38 +0000 | [diff] [blame] | 434 | struct ofprop prop; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 435 | data = dev_read_prop(config, "rockchip,pins", &count); |
| 436 | if (count < 0) { |
| 437 | debug("%s: bad array size %d\n", __func__, count); |
| 438 | return -EINVAL; |
| 439 | } |
| 440 | |
| 441 | count /= sizeof(u32); |
| 442 | if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { |
| 443 | debug("%s: unsupported pins array count %d\n", |
| 444 | __func__, count); |
| 445 | return -EINVAL; |
| 446 | } |
| 447 | |
| 448 | for (i = 0; i < count; i++) |
| 449 | cells[i] = fdt32_to_cpu(data[i]); |
| 450 | |
| 451 | for (i = 0; i < (count >> 2); i++) { |
| 452 | bank = cells[4 * i + 0]; |
| 453 | pin = cells[4 * i + 1]; |
| 454 | mux = cells[4 * i + 2]; |
| 455 | conf = cells[4 * i + 3]; |
| 456 | |
| 457 | ret = rockchip_verify_config(dev, bank, pin); |
| 458 | if (ret) |
| 459 | return ret; |
| 460 | |
| 461 | ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); |
| 462 | if (ret) |
| 463 | return ret; |
| 464 | |
| 465 | node = ofnode_get_by_phandle(conf); |
| 466 | if (!ofnode_valid(node)) |
| 467 | return -ENODEV; |
Jonas Karlman | 420b010 | 2023-06-08 10:59:38 +0000 | [diff] [blame] | 468 | ofnode_for_each_prop(prop, node) { |
| 469 | value = ofprop_get_property(&prop, &prop_name, &prop_len); |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 470 | if (!value) |
Jonas Karlman | 420b010 | 2023-06-08 10:59:38 +0000 | [diff] [blame] | 471 | continue; |
| 472 | |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 473 | param = rockchip_pinconf_prop_name_to_param(prop_name, |
| 474 | &default_val); |
| 475 | if (param < 0) |
Jonas Karlman | 420b010 | 2023-06-08 10:59:38 +0000 | [diff] [blame] | 476 | continue; |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 477 | |
| 478 | if (prop_len >= sizeof(fdt32_t)) |
| 479 | arg = fdt32_to_cpu(*(fdt32_t *)value); |
| 480 | else |
| 481 | arg = default_val; |
| 482 | |
| 483 | ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, |
| 484 | param, arg); |
| 485 | if (ret) { |
| 486 | debug("%s: rockchip_pinconf_set fail: %d\n", |
| 487 | __func__, ret); |
| 488 | return ret; |
| 489 | } |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | return 0; |
| 494 | } |
| 495 | |
| 496 | const struct pinctrl_ops rockchip_pinctrl_ops = { |
| 497 | .set_state = rockchip_pinctrl_set_state, |
| 498 | .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, |
| 499 | }; |
| 500 | |
| 501 | /* retrieve the soc specific data */ |
| 502 | static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) |
| 503 | { |
| 504 | struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); |
| 505 | struct rockchip_pin_ctrl *ctrl = |
| 506 | (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); |
| 507 | struct rockchip_pin_bank *bank; |
| 508 | int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; |
| 509 | |
| 510 | grf_offs = ctrl->grf_mux_offset; |
| 511 | pmu_offs = ctrl->pmu_mux_offset; |
| 512 | drv_pmu_offs = ctrl->pmu_drv_offset; |
| 513 | drv_grf_offs = ctrl->grf_drv_offset; |
| 514 | bank = ctrl->pin_banks; |
| 515 | |
| 516 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { |
| 517 | int bank_pins = 0; |
| 518 | |
| 519 | bank->priv = priv; |
| 520 | bank->pin_base = ctrl->nr_pins; |
| 521 | ctrl->nr_pins += bank->nr_pins; |
| 522 | |
| 523 | /* calculate iomux and drv offsets */ |
| 524 | for (j = 0; j < 4; j++) { |
| 525 | struct rockchip_iomux *iom = &bank->iomux[j]; |
| 526 | struct rockchip_drv *drv = &bank->drv[j]; |
| 527 | int inc; |
| 528 | |
| 529 | if (bank_pins >= bank->nr_pins) |
| 530 | break; |
| 531 | |
| 532 | /* preset iomux offset value, set new start value */ |
| 533 | if (iom->offset >= 0) { |
| 534 | if (iom->type & IOMUX_SOURCE_PMU) |
| 535 | pmu_offs = iom->offset; |
| 536 | else |
| 537 | grf_offs = iom->offset; |
| 538 | } else { /* set current iomux offset */ |
| 539 | iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? |
| 540 | pmu_offs : grf_offs; |
| 541 | } |
| 542 | |
| 543 | /* preset drv offset value, set new start value */ |
| 544 | if (drv->offset >= 0) { |
| 545 | if (iom->type & IOMUX_SOURCE_PMU) |
| 546 | drv_pmu_offs = drv->offset; |
| 547 | else |
| 548 | drv_grf_offs = drv->offset; |
| 549 | } else { /* set current drv offset */ |
| 550 | drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? |
| 551 | drv_pmu_offs : drv_grf_offs; |
| 552 | } |
| 553 | |
| 554 | debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", |
| 555 | i, j, iom->offset, drv->offset); |
| 556 | |
| 557 | /* |
| 558 | * Increase offset according to iomux width. |
| 559 | * 4bit iomux'es are spread over two registers. |
| 560 | */ |
| 561 | inc = (iom->type & (IOMUX_WIDTH_4BIT | |
David Wu | fd2fdf7 | 2019-12-03 19:26:50 +0800 | [diff] [blame] | 562 | IOMUX_WIDTH_3BIT | |
| 563 | IOMUX_8WIDTH_2BIT)) ? 8 : 4; |
Jagan Teki | 9e0e681 | 2022-12-14 23:20:56 +0530 | [diff] [blame] | 564 | if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) |
David Wu | 5f596ae | 2019-01-02 21:00:55 +0800 | [diff] [blame] | 565 | pmu_offs += inc; |
| 566 | else |
| 567 | grf_offs += inc; |
| 568 | |
| 569 | /* |
| 570 | * Increase offset according to drv width. |
| 571 | * 3bit drive-strenth'es are spread over two registers. |
| 572 | */ |
| 573 | if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || |
| 574 | (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) |
| 575 | inc = 8; |
| 576 | else |
| 577 | inc = 4; |
| 578 | |
| 579 | if (iom->type & IOMUX_SOURCE_PMU) |
| 580 | drv_pmu_offs += inc; |
| 581 | else |
| 582 | drv_grf_offs += inc; |
| 583 | |
| 584 | bank_pins += 8; |
| 585 | } |
| 586 | |
| 587 | /* calculate the per-bank recalced_mask */ |
| 588 | for (j = 0; j < ctrl->niomux_recalced; j++) { |
| 589 | int pin = 0; |
| 590 | |
| 591 | if (ctrl->iomux_recalced[j].num == bank->bank_num) { |
| 592 | pin = ctrl->iomux_recalced[j].pin; |
| 593 | bank->recalced_mask |= BIT(pin); |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | /* calculate the per-bank route_mask */ |
| 598 | for (j = 0; j < ctrl->niomux_routes; j++) { |
| 599 | int pin = 0; |
| 600 | |
| 601 | if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { |
| 602 | pin = ctrl->iomux_routes[j].pin; |
| 603 | bank->route_mask |= BIT(pin); |
| 604 | } |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | return ctrl; |
| 609 | } |
| 610 | |
| 611 | int rockchip_pinctrl_probe(struct udevice *dev) |
| 612 | { |
| 613 | struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); |
| 614 | struct rockchip_pin_ctrl *ctrl; |
| 615 | struct udevice *syscon; |
| 616 | struct regmap *regmap; |
| 617 | int ret = 0; |
| 618 | |
| 619 | /* get rockchip grf syscon phandle */ |
| 620 | ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", |
| 621 | &syscon); |
| 622 | if (ret) { |
| 623 | debug("unable to find rockchip,grf syscon device (%d)\n", ret); |
| 624 | return ret; |
| 625 | } |
| 626 | |
| 627 | /* get grf-reg base address */ |
| 628 | regmap = syscon_get_regmap(syscon); |
| 629 | if (!regmap) { |
| 630 | debug("unable to find rockchip grf regmap\n"); |
| 631 | return -ENODEV; |
| 632 | } |
| 633 | priv->regmap_base = regmap; |
| 634 | |
| 635 | /* option: get pmu-reg base address */ |
| 636 | ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", |
| 637 | &syscon); |
| 638 | if (!ret) { |
| 639 | /* get pmugrf-reg base address */ |
| 640 | regmap = syscon_get_regmap(syscon); |
| 641 | if (!regmap) { |
| 642 | debug("unable to find rockchip pmu regmap\n"); |
| 643 | return -ENODEV; |
| 644 | } |
| 645 | priv->regmap_pmu = regmap; |
| 646 | } |
| 647 | |
| 648 | ctrl = rockchip_pinctrl_get_soc_data(dev); |
| 649 | if (!ctrl) { |
| 650 | debug("driver data not available\n"); |
| 651 | return -EINVAL; |
| 652 | } |
| 653 | |
| 654 | priv->ctrl = ctrl; |
| 655 | return 0; |
| 656 | } |