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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shengzhou Liu11ff48a2014-04-18 16:43:40 +08002/* Copyright 2013 Freescale Semiconductor, Inc.
Shengzhou Liu11ff48a2014-04-18 16:43:40 +08003 */
4
Tom Rinidec7ea02024-05-20 13:35:03 -06005#include <config.h>
Simon Glass85d65312019-12-28 10:44:58 -07006#include <clock_legacy.h>
Simon Glassa73bda42015-11-08 23:47:45 -07007#include <console.h>
Simon Glass9d1f6192019-08-02 09:44:25 -06008#include <env_internal.h>
Simon Glass284f71b2019-12-28 10:44:45 -07009#include <init.h>
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080010#include <malloc.h>
11#include <ns16550.h>
12#include <nand.h>
13#include <i2c.h>
14#include <mmc.h>
15#include <fsl_esdhc.h>
16#include <spi_flash.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060017#include <asm/global_data.h>
Simon Glassdd8e2242016-09-24 18:20:10 -060018#include "../common/spl.h"
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080019
20DECLARE_GLOBAL_DATA_PTR;
21
22phys_size_t get_effective_memsize(void)
23{
24 return CONFIG_SYS_L3_SIZE;
25}
26
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080027void board_init_f(ulong bootflag)
28{
29 u32 plat_ratio, sys_clk, ccb_clk;
Tom Rinid5c3bf22022-10-28 20:27:12 -040030 ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080031
32 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
33 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
34
35 /* Update GD pointer */
36 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
37
38 console_init_f();
39
40 /* initialize selected port with appropriate baud rate */
Tom Rini8c70baa2021-12-14 13:36:40 -050041 sys_clk = get_board_sys_clk();
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080042 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
43 ccb_clk = sys_clk * plat_ratio / 2;
44
Tom Rinidf6a2152022-11-16 13:10:28 -050045 ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080046 ccb_clk / 16 / CONFIG_BAUDRATE);
47
48#if defined(CONFIG_SPL_MMC_BOOT)
49 puts("\nSD boot...\n");
50#elif defined(CONFIG_SPL_SPI_BOOT)
51 puts("\nSPI boot...\n");
52#elif defined(CONFIG_SPL_NAND_BOOT)
53 puts("\nNAND boot...\n");
54#endif
55
56 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
57}
58
59void board_init_r(gd_t *gd, ulong dest_addr)
60{
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090061 struct bd_info *bd;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080062
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090063 bd = (struct bd_info *)(gd + sizeof(gd_t));
64 memset(bd, 0, sizeof(struct bd_info));
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080065 gd->bd = bd;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080066
Simon Glass302445a2017-01-23 13:31:22 -070067 arch_cpu_init();
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080068 get_clocks();
69 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
70 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garg2ff056b2016-05-25 12:41:48 -040071 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080072
73#ifdef CONFIG_SPL_NAND_BOOT
74 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -050075 (uchar *)SPL_ENV_ADDR);
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080076#endif
77#ifdef CONFIG_SPL_MMC_BOOT
78 mmc_initialize(bd);
79 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -050080 (uchar *)SPL_ENV_ADDR);
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080081#endif
82#ifdef CONFIG_SPL_SPI_BOOT
Simon Glassdd8e2242016-09-24 18:20:10 -060083 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -050084 (uchar *)SPL_ENV_ADDR);
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080085#endif
86
Tom Rini5cd7ece2019-11-18 20:02:10 -050087 gd->env_addr = (ulong)(SPL_ENV_ADDR);
Simon Glass4bc2ad22017-08-03 12:21:56 -060088 gd->env_valid = ENV_VALID;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080089
90 i2c_init_all();
91
Simon Glassd35f3382017-04-06 12:47:05 -060092 dram_init();
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080093
94#ifdef CONFIG_SPL_MMC_BOOT
95 mmc_boot();
96#elif defined(CONFIG_SPL_SPI_BOOT)
Simon Glassdd8e2242016-09-24 18:20:10 -060097 fsl_spi_boot();
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080098#elif defined(CONFIG_SPL_NAND_BOOT)
99 nand_boot();
100#endif
101}