blob: 196d56dc17d35b5a312d2a0d71bd5d35dc15faa5 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChung Liewe7e4fc82008-10-22 11:38:21 +00002/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wang35d23df2012-03-26 21:49:05 +00006 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
TsiChung Liewe7e4fc82008-10-22 11:38:21 +00007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +00008 */
9
10#include <config.h>
Simon Glass0ffd9db2019-12-28 10:45:06 -070011#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000013#include <asm/immap.h>
Alison Wang35d23df2012-03-26 21:49:05 +000014#include <asm/io.h>
Simon Glassdbd79542020-05-10 11:40:11 -060015#include <linux/delay.h>
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000016
17DECLARE_GLOBAL_DATA_PTR;
18
19int checkboard(void)
20{
21 puts("Board: ");
22 puts("Freescale M53017EVB\n");
23 return 0;
24};
25
Simon Glassd35f3382017-04-06 12:47:05 -060026int dram_init(void)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000027{
Alison Wang35d23df2012-03-26 21:49:05 +000028 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000029 u32 dramsize, i;
30
Tom Rinibb4dd962022-11-16 13:10:37 -050031 dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000032
33 for (i = 0x13; i < 0x20; i++) {
34 if (dramsize == (1 << i))
35 break;
36 }
37 i--;
38
Tom Rinibb4dd962022-11-16 13:10:37 -050039 out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
40#ifdef CFG_SYS_SDRAM_BASE1
41 out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000042#endif
Tom Rinibb4dd962022-11-16 13:10:37 -050043 out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
44 out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000045
46 udelay(500);
47
48 /* Issue PALL */
Tom Rinibb4dd962022-11-16 13:10:37 -050049 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000050 asm("nop");
51
52 /* Perform two refresh cycles */
Tom Rinibb4dd962022-11-16 13:10:37 -050053 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
54 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000055 asm("nop");
56
57 /* Issue LEMR */
Tom Rinibb4dd962022-11-16 13:10:37 -050058 out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000059 asm("nop");
Tom Rinibb4dd962022-11-16 13:10:37 -050060 out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000061 asm("nop");
62
Tom Rinibb4dd962022-11-16 13:10:37 -050063 out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000064 asm("nop");
65
Alison Wang35d23df2012-03-26 21:49:05 +000066 out_be32(&sdram->ctrl,
Tom Rinibb4dd962022-11-16 13:10:37 -050067 (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000068 asm("nop");
69
70 udelay(100);
71
Simon Glass39f90ba2017-03-31 08:40:25 -060072 gd->ram_size = dramsize;
73
74 return 0;
TsiChung Liewe7e4fc82008-10-22 11:38:21 +000075};
76
77int testdram(void)
78{
79 /* TODO: XXX XXX XXX */
80 printf("DRAM test not implemented!\n");
81
82 return (0);
83}