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Yuantian Tang4aefa162019-04-10 16:43:33 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
Tom Rinidec7ea02024-05-20 13:35:03 -06006#include <config.h>
7#include <linux/kernel.h>
Yuantian Tang4aefa162019-04-10 16:43:33 +08008#include <asm/arch/fsl_serdes.h>
9
10struct serdes_config {
11 u32 protocol;
12 u8 lanes[SRDS_MAX_LANES];
13 u8 rcw_lanes[SRDS_MAX_LANES];
14};
15
16static struct serdes_config serdes1_cfg_tbl[] = {
17 /* SerDes 1 */
18 {0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} },
19 {0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} },
20 {0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} },
21 {0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} },
22 {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
23 {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },
24 {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },
25 {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
Xiaowei Bao1eb44592019-05-21 18:28:31 +080026 {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
27 {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
Hou Zhiqiangd24328a2019-09-04 06:25:44 +000028 {0xBB31, {SXGMII1, QXGMII2, PCIE2, PCIE1} },
Xiaowei Bao1eb44592019-05-21 18:28:31 +080029 {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
30 {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
31 {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },
32 {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} },
33 {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} },
34 {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} },
35 {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} },
36 {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} },
37 {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} },
38 {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} },
Alex Margineanc3691612020-01-10 23:51:32 +020039 {0x7777, {SGMII1, SGMII2, SGMII3, SGMII4} },
40 {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
41 {0xb998, {SGMII_T1, SGMII2, SGMII3, PCIE1} },
42 {0xbb56, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} },
Yuantian Tang4aefa162019-04-10 16:43:33 +080043 {}
44};
45
46static struct serdes_config *serdes_cfg_tbl[] = {
47 serdes1_cfg_tbl,
48};
49
50enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
51{
52 struct serdes_config *ptr;
53
54 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
55 return 0;
56
57 ptr = serdes_cfg_tbl[serdes];
58 while (ptr->protocol) {
59 if (ptr->protocol == cfg)
60 return ptr->lanes[lane];
61 ptr++;
62 }
63
64 return 0;
65}
66
67int is_serdes_prtcl_valid(int serdes, u32 prtcl)
68{
69 int i;
70 struct serdes_config *ptr;
71
72 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
73 return 0;
74
75 ptr = serdes_cfg_tbl[serdes];
76 while (ptr->protocol) {
77 if (ptr->protocol == prtcl)
78 break;
79 ptr++;
80 }
81
82 if (!ptr->protocol)
83 return 0;
84
85 for (i = 0; i < SRDS_MAX_LANES; i++) {
86 if (ptr->lanes[i] != NONE)
87 return 1;
88 }
89
90 return 0;
91}