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git01.mediatek.com / filogic / uboot / df1d94b54383001005d2fa1cee5574fc6dd23cfc / . / arch / arm / include / asm / arch-mx7 / clock_slice.h
blob: 9a7c1f8237a8300e874602cd4ce6fdd68abd78e3 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Adrian Alonsoeed22a02015-09-02 13:54:18 -0500[diff] [blame]2/*
3 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
4 *
5 * Author:
6 * Peng Fan <Peng.Fan@freescale.com>
Adrian Alonsoeed22a02015-09-02 13:54:18 -0500[diff] [blame]7 */
8
9#ifndef _ASM_ARCH_CLOCK_SLICE_H
10#define _ASM_ARCH_CLOCK_SLICE_H
11
12enum root_pre_div {
13 CLK_ROOT_PRE_DIV1 = 0,
14 CLK_ROOT_PRE_DIV2,
15 CLK_ROOT_PRE_DIV3,
16 CLK_ROOT_PRE_DIV4,
17 CLK_ROOT_PRE_DIV5,
18 CLK_ROOT_PRE_DIV6,
19 CLK_ROOT_PRE_DIV7,
20 CLK_ROOT_PRE_DIV8,
21};
22
23enum root_post_div {
24 CLK_ROOT_POST_DIV1 = 0,
25 CLK_ROOT_POST_DIV2,
26 CLK_ROOT_POST_DIV3,
27 CLK_ROOT_POST_DIV4,
28 CLK_ROOT_POST_DIV5,
29 CLK_ROOT_POST_DIV6,
30 CLK_ROOT_POST_DIV7,
31 CLK_ROOT_POST_DIV8,
32 CLK_ROOT_POST_DIV9,
33 CLK_ROOT_POST_DIV10,
34 CLK_ROOT_POST_DIV11,
35 CLK_ROOT_POST_DIV12,
36 CLK_ROOT_POST_DIV13,
37 CLK_ROOT_POST_DIV14,
38 CLK_ROOT_POST_DIV15,
39 CLK_ROOT_POST_DIV16,
40 CLK_ROOT_POST_DIV17,
41 CLK_ROOT_POST_DIV18,
42 CLK_ROOT_POST_DIV19,
43 CLK_ROOT_POST_DIV20,
44 CLK_ROOT_POST_DIV21,
45 CLK_ROOT_POST_DIV22,
46 CLK_ROOT_POST_DIV23,
47 CLK_ROOT_POST_DIV24,
48 CLK_ROOT_POST_DIV25,
49 CLK_ROOT_POST_DIV26,
50 CLK_ROOT_POST_DIV27,
51 CLK_ROOT_POST_DIV28,
52 CLK_ROOT_POST_DIV29,
53 CLK_ROOT_POST_DIV30,
54 CLK_ROOT_POST_DIV31,
55 CLK_ROOT_POST_DIV32,
56 CLK_ROOT_POST_DIV33,
57 CLK_ROOT_POST_DIV34,
58 CLK_ROOT_POST_DIV35,
59 CLK_ROOT_POST_DIV36,
60 CLK_ROOT_POST_DIV37,
61 CLK_ROOT_POST_DIV38,
62 CLK_ROOT_POST_DIV39,
63 CLK_ROOT_POST_DIV40,
64 CLK_ROOT_POST_DIV41,
65 CLK_ROOT_POST_DIV42,
66 CLK_ROOT_POST_DIV43,
67 CLK_ROOT_POST_DIV44,
68 CLK_ROOT_POST_DIV45,
69 CLK_ROOT_POST_DIV46,
70 CLK_ROOT_POST_DIV47,
71 CLK_ROOT_POST_DIV48,
72 CLK_ROOT_POST_DIV49,
73 CLK_ROOT_POST_DIV50,
74 CLK_ROOT_POST_DIV51,
75 CLK_ROOT_POST_DIV52,
76 CLK_ROOT_POST_DIV53,
77 CLK_ROOT_POST_DIV54,
78 CLK_ROOT_POST_DIV55,
79 CLK_ROOT_POST_DIV56,
80 CLK_ROOT_POST_DIV57,
81 CLK_ROOT_POST_DIV58,
82 CLK_ROOT_POST_DIV59,
83 CLK_ROOT_POST_DIV60,
84 CLK_ROOT_POST_DIV61,
85 CLK_ROOT_POST_DIV62,
86 CLK_ROOT_POST_DIV63,
87 CLK_ROOT_POST_DIV64,
88};
89
90enum root_auto_div {
91 CLK_ROOT_AUTO_DIV1 = 0,
92 CLK_ROOT_AUTO_DIV2,
93 CLK_ROOT_AUTO_DIV4,
94 CLK_ROOT_AUTO_DIV8,
95 CLK_ROOT_AUTO_DIV16,
96};
97
98int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src);
99int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
100int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div);
101int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
102int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div);
103int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div);
104int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
105 int auto_en);
106int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
107 int *auto_en);
108int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
109int clock_set_target_val(enum clk_root_index clock_id, u32 val);
110int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
111 enum root_post_div post_div, enum clk_root_src clock_src);
112int clock_root_enabled(enum clk_root_index clock_id);
113
114int clock_enable(enum clk_ccgr_index index, bool enable);
115#endif