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Peng Fanc2055a52018-10-18 14:28:14 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
Gaurav Jaindb4dd6a2022-03-24 11:50:33 +05303 * Copyright 2018, 2021 NXP
Peng Fanc2055a52018-10-18 14:28:14 +02004 */
5
6#ifndef __ASM_ARCH_IMX8_REGS_H__
7#define __ASM_ARCH_IMX8_REGS_H__
8
Peng Fan00565bf2019-05-09 08:33:55 +00009#define ARCH_MXC
10
Peng Fanc2055a52018-10-18 14:28:14 +020011#define LPUART_BASE 0x5A060000
12
13#define GPT1_BASE_ADDR 0x5D140000
14#define SCU_LPUART_BASE 0x33220000
15#define GPIO1_BASE_ADDR 0x5D080000
16#define GPIO2_BASE_ADDR 0x5D090000
17#define GPIO3_BASE_ADDR 0x5D0A0000
18#define GPIO4_BASE_ADDR 0x5D0B0000
19#define GPIO5_BASE_ADDR 0x5D0C0000
20#define GPIO6_BASE_ADDR 0x5D0D0000
21#define GPIO7_BASE_ADDR 0x5D0E0000
22#define GPIO8_BASE_ADDR 0x5D0F0000
23#define LPI2C1_BASE_ADDR 0x5A800000
24#define LPI2C2_BASE_ADDR 0x5A810000
25#define LPI2C3_BASE_ADDR 0x5A820000
26#define LPI2C4_BASE_ADDR 0x5A830000
27#define LPI2C5_BASE_ADDR 0x5A840000
28
Oleksandr Suvorovcfa3ac12021-02-09 10:38:12 +020029#define FEC_QUIRK_ENET_MAC
30
Peng Fanc2055a52018-10-18 14:28:14 +020031#ifdef CONFIG_IMX8QXP
32#define LVDS0_PHYCTRL_BASE 0x56221000
33#define LVDS1_PHYCTRL_BASE 0x56241000
34#define MIPI0_SS_BASE 0x56220000
35#define MIPI1_SS_BASE 0x56240000
36#endif
37
38#define APBH_DMA_ARB_BASE_ADDR 0x5B810000
39#define APBH_DMA_ARB_END_ADDR 0x5B81FFFF
40#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
41
42#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
43#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
44
45#define PASS_OVER_INFO_ADDR 0x0010fe00
46
47#define USB_BASE_ADDR 0x5b0d0000
48#define USB_PHY0_BASE_ADDR 0x5b100000
49
Tom Rini376b88a2022-10-28 20:27:13 -040050#define CFG_SYS_FSL_SEC_ADDR (0x31400000)
Gaurav Jaindb4dd6a2022-03-24 11:50:33 +053051
Peng Fanc2055a52018-10-18 14:28:14 +020052#endif /* __ASM_ARCH_IMX8_REGS_H__ */