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git01.mediatek.com / filogic / uboot / df1d94b54383001005d2fa1cee5574fc6dd23cfc / . / arch / arm / include / asm / arch-aspeed / scu_ast2600.h
blob: a2c8852db842d6877f3bda6e5257c347a97063f4 [file] [log] [blame]
Ryan Chence5ecc12020-12-14 13:54:23 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (c) Aspeed Technology Inc.
4 */
5#ifndef _ASM_ARCH_SCU_AST2600_H
6#define _ASM_ARCH_SCU_AST2600_H
7
8#define SCU_UNLOCK_KEY 0x1688a8a8
9
10#define SCU_CLKGATE1_EMMC BIT(27)
Chia-Wei Wangb0e3cf92021-10-27 14:17:29 +0800[diff] [blame]11#define SCU_CLKGATE1_ACRY BIT(24)
Ryan Chence5ecc12020-12-14 13:54:23 +0800[diff] [blame]12#define SCU_CLKGATE1_MAC2 BIT(21)
13#define SCU_CLKGATE1_MAC1 BIT(20)
Joel Stanleyd59cd6f2021-10-27 14:17:26 +0800[diff] [blame]14#define SCU_CLKGATE1_USB_HUB BIT(14)
15#define SCU_CLKGATE1_HACE BIT(13)
16#define SCU_CLKGATE1_USB_HOST2 BIT(7)
Ryan Chence5ecc12020-12-14 13:54:23 +0800[diff] [blame]17
18#define SCU_CLKGATE2_FSI BIT(30)
19#define SCU_CLKGATE2_MAC4 BIT(21)
20#define SCU_CLKGATE2_MAC3 BIT(20)
21#define SCU_CLKGATE2_SDIO BIT(4)
22
23#define SCU_DRAM_HDSHK_SOC_INIT BIT(7)
24#define SCU_DRAM_HDSHK_RDY BIT(6)
25
26#define SCU_CLKSRC1_ECC_RSA_DIV_MASK GENMASK(27, 26)
27#define SCU_CLKSRC1_ECC_RSA_DIV_SHIFT 26
28#define SCU_CLKSRC1_PCLK_DIV_MASK GENMASK(25, 23)
29#define SCU_CLKSRC1_PCLK_DIV_SHIFT 23
30#define SCU_CLKSRC1_BCLK_DIV_MASK GENMASK(22, 20)
31#define SCU_CLKSRC1_BCLK_DIV_SHIFT 20
32#define SCU_CLKSRC1_ECC_RSA BIT(19)
33#define SCU_CLKSRC1_MAC_DIV_MASK GENMASK(18, 16)
34#define SCU_CLKSRC1_MAC_DIV_SHIFT 16
35#define SCU_CLKSRC1_EMMC_EN BIT(15)
36#define SCU_CLKSRC1_EMMC_DIV_MASK GENMASK(14, 12)
37#define SCU_CLKSRC1_EMMC_DIV_SHIFT 12
38#define SCU_CLKSRC1_EMMC BIT(11)
39
40#define SCU_CLKSRC2_RMII12 BIT(19)
41#define SCU_CLKSRC2_RMII12_DIV_MASK GENMASK(18, 16)
42#define SCU_CLKSRC2_RMII12_DIV_SHIFT 16
43#define SCU_CLKSRC2_UART5 BIT(14)
44
45#define SCU_CLKSRC4_SDIO_EN BIT(31)
46#define SCU_CLKSRC4_SDIO_DIV_MASK GENMASK(30, 28)
47#define SCU_CLKSRC4_SDIO_DIV_SHIFT 28
48#define SCU_CLKSRC4_MAC_DIV_MASK GENMASK(26, 24)
49#define SCU_CLKSRC4_MAC_DIV_SHIFT 24
50#define SCU_CLKSRC4_RMII34_DIV_MASK GENMASK(18, 16)
51#define SCU_CLKSRC4_RMII34_DIV_SHIFT 16
52#define SCU_CLKSRC4_PCLK_DIV_MASK GENMASK(11, 9)
53#define SCU_CLKSRC4_PCLK_DIV_SHIFT 9
54#define SCU_CLKSRC4_SDIO BIT(8)
55#define SCU_CLKSRC4_UART6 BIT(5)
56#define SCU_CLKSRC4_UART4 BIT(3)
57#define SCU_CLKSRC4_UART3 BIT(2)
58#define SCU_CLKSRC4_UART2 BIT(1)
59#define SCU_CLKSRC4_UART1 BIT(0)
60
61#define SCU_CLKSRC5_UART13 BIT(12)
62#define SCU_CLKSRC5_UART12 BIT(11)
63#define SCU_CLKSRC5_UART11 BIT(10)
64#define SCU_CLKSRC5_UART10 BIT(9)
65#define SCU_CLKSRC5_UART9 BIT(8)
66#define SCU_CLKSRC5_UART8 BIT(7)
67#define SCU_CLKSRC5_UART7 BIT(6)
68#define SCU_CLKSRC5_HUXCLK_MASK GENMASK(5, 3)
69#define SCU_CLKSRC5_HUXCLK_SHIFT 3
70#define SCU_CLKSRC5_UXCLK_MASK GENMASK(2, 0)
71#define SCU_CLKSRC5_UXCLK_SHIFT 0
72
73#define SCU_PINCTRL1_EMMC_MASK GENMASK(31, 24)
74#define SCU_PINCTRL1_EMMC_SHIFT 24
75
76#define SCU_PINCTRL16_MAC4_DRIVING_MASK GENMASK(3, 2)
77#define SCU_PINCTRL16_MAC4_DRIVING_SHIFT 2
78#define SCU_PINCTRL16_MAC3_DRIVING_MASK GENMASK(1, 0)
79#define SCU_PINCTRL16_MAC3_DRIVING_SHIFT 0
80
81#define SCU_HWSTRAP1_CPU_AXI_CLK_RATIO BIT(16)
82#define SCU_HWSTRAP1_VGA_MEM_MASK GENMASK(14, 13)
83#define SCU_HWSTRAP1_VGA_MEM_SHIFT 13
84#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK GENMASK(12, 11)
85#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT 11
86#define SCU_HWSTRAP1_CPU_FREQ_MASK GENMASK(10, 8)
87#define SCU_HWSTRAP1_CPU_FREQ_SHIFT 8
88#define SCU_HWSTRAP1_MAC2_INTF BIT(7)
89#define SCU_HWSTRAP1_MAC1_INTF BIT(6)
Chia-Wei Wang28263592022-06-01 16:43:52 +0800[diff] [blame]90#define SCU_HWSTRAP1_BOOT_EMMC BIT(2)
91
92#define SCU_HWSTRAP2_BOOT_UART BIT(8)
Ryan Chence5ecc12020-12-14 13:54:23 +0800[diff] [blame]93
94#define SCU_EFUSE_DIS_DP BIT(17)
95#define SCU_EFUSE_DIS_VGA BIT(14)
96#define SCU_EFUSE_DIS_PCIE_EP BIT(13)
97#define SCU_EFUSE_DIS_USB BIT(12)
98#define SCU_EFUSE_DIS_RVAS BIT(10)
99#define SCU_EFUSE_DIS_VIDEO_DEC BIT(9)
100#define SCU_EFUSE_DIS_VIDEO BIT(8)
101#define SCU_EFUSE_DIS_PCIE_RC BIT(7)
102#define SCU_EFUSE_DIS_CM3 BIT(6)
103#define SCU_EFUSE_DIS_CA7 BIT(5)
104
105#define SCU_PLL_RST BIT(25)
106#define SCU_PLL_BYPASS BIT(24)
107#define SCU_PLL_OFF BIT(23)
108#define SCU_PLL_DIV_MASK GENMASK(22, 19)
109#define SCU_PLL_DIV_SHIFT 19
110#define SCU_PLL_DENUM_MASK GENMASK(18, 13)
111#define SCU_PLL_DENUM_SHIFT 13
112#define SCU_PLL_NUM_MASK GENMASK(12, 0)
113#define SCU_PLL_NUM_SHIFT 0
114
115#define SCU_UART_CLKGEN_N_MASK GENMASK(17, 8)
116#define SCU_UART_CLKGEN_N_SHIFT 8
117#define SCU_UART_CLKGEN_R_MASK GENMASK(7, 0)
118#define SCU_UART_CLKGEN_R_SHIFT 0
119
120#define SCU_HUART_CLKGEN_N_MASK GENMASK(17, 8)
121#define SCU_HUART_CLKGEN_N_SHIFT 8
122#define SCU_HUART_CLKGEN_R_MASK GENMASK(7, 0)
123#define SCU_HUART_CLKGEN_R_SHIFT 0
124
125#define SCU_MISC_CTRL1_UART5_DIV BIT(12)
126
127#ifndef __ASSEMBLY__
Tom Rinidec7ea02024-05-20 13:35:03 -0600[diff] [blame]128#include <linux/types.h>
129
Ryan Chence5ecc12020-12-14 13:54:23 +0800[diff] [blame]130struct ast2600_scu {
131 uint32_t prot_key1; /* 0x000 */
132 uint32_t chip_id1; /* 0x004 */
133 uint32_t rsv_0x08; /* 0x008 */
134 uint32_t rsv_0x0c; /* 0x00C */
135 uint32_t prot_key2; /* 0x010 */
136 uint32_t chip_id2; /* 0x014 */
137 uint32_t rsv_0x18[10]; /* 0x018 ~ 0x03C */
138 uint32_t modrst_ctrl1; /* 0x040 */
139 uint32_t modrst_clr1; /* 0x044 */
140 uint32_t rsv_0x48; /* 0x048 */
141 uint32_t rsv_0x4C; /* 0x04C */
142 uint32_t modrst_ctrl2; /* 0x050 */
143 uint32_t modrst_clr2; /* 0x054 */
144 uint32_t rsv_0x58; /* 0x058 */
145 uint32_t rsv_0x5C; /* 0x05C */
146 uint32_t extrst_sel1; /* 0x060 */
147 uint32_t sysrst_sts1_1; /* 0x064 */
148 uint32_t sysrst_sts1_2; /* 0x068 */
149 uint32_t sysrst_sts1_3; /* 0x06C */
150 uint32_t extrst_sel2; /* 0x070 */
151 uint32_t sysrst_sts2_1; /* 0x074 */
152 uint32_t sysrst_sts2_2; /* 0x078 */
153 uint32_t stsrst_sts3_2; /* 0x07C */
154 uint32_t clkgate_ctrl1; /* 0x080 */
155 uint32_t clkgate_clr1; /* 0x084 */
156 uint32_t rsv_0x88; /* 0x088 */
157 uint32_t rsv_0x8C; /* 0x08C */
158 uint32_t clkgate_ctrl2; /* 0x090 */
159 uint32_t clkgate_clr2; /* 0x094 */
160 uint32_t rsv_0x98[10]; /* 0x098 ~ 0x0BC */
161 uint32_t misc_ctrl1; /* 0x0C0 */
162 uint32_t misc_ctrl2; /* 0x0C4 */
163 uint32_t debug_ctrl1; /* 0x0C8 */
164 uint32_t rsv_0xCC; /* 0x0CC */
165 uint32_t misc_ctrl3; /* 0x0D0 */
166 uint32_t misc_ctrl4; /* 0x0D4 */
167 uint32_t debug_ctrl2; /* 0x0D8 */
168 uint32_t rsv_0xdc[9]; /* 0x0DC ~ 0x0FC */
169 uint32_t dram_hdshk; /* 0x100 */
170 uint32_t soc_scratch[3]; /* 0x104 ~ 0x10C */
171 uint32_t rsv_0x110[4]; /* 0x110 ~ 0x11C*/
172 uint32_t cpu_scratch_wp; /* 0x120 */
173 uint32_t rsv_0x124[23]; /* 0x124 */
174 uint32_t smp_boot[12]; /* 0x180 */
175 uint32_t cpu_scratch[20]; /* 0x1b0 */
176 uint32_t hpll; /* 0x200 */
177 uint32_t hpll_ext; /* 0x204 */
178 uint32_t rsv_0x208[2]; /* 0x208 ~ 0x20C */
179 uint32_t apll; /* 0x210 */
180 uint32_t apll_ext; /* 0x214 */
181 uint32_t rsv_0x218[2]; /* 0x218 ~ 0x21C */
182 uint32_t mpll; /* 0x220 */
183 uint32_t mpll_ext; /* 0x224 */
184 uint32_t rsv_0x228[6]; /* 0x228 ~ 0x23C */
185 uint32_t epll; /* 0x240 */
186 uint32_t epll_ext; /* 0x244 */
187 uint32_t rsv_0x248[6]; /* 0x248 ~ 0x25C */
188 uint32_t dpll; /* 0x260 */
189 uint32_t dpll_ext; /* 0x264 */
190 uint32_t rsv_0x268[38]; /* 0x268 ~ 0x2FC */
191 uint32_t clksrc1; /* 0x300 */
192 uint32_t clksrc2; /* 0x304 */
193 uint32_t clksrc3; /* 0x308 */
194 uint32_t rsv_0x30c; /* 0x30C */
195 uint32_t clksrc4; /* 0x310 */
196 uint32_t clksrc5; /* 0x314 */
197 uint32_t rsv_0x318[2]; /* 0x318 ~ 0x31C */
198 uint32_t freq_counter_ctrl1; /* 0x320 */
199 uint32_t freq_counter_cmp1; /* 0x324 */
200 uint32_t rsv_0x328[2]; /* 0x328 ~ 0x32C */
201 uint32_t freq_counter_ctrl2; /* 0x330 */
202 uint32_t freq_counter_cmp2; /* 0x334 */
203 uint32_t uart_clkgen; /* 0x338 */
204 uint32_t huart_clkgen; /* 0x33C */
205 uint32_t mac12_clk_delay; /* 0x340 */
206 uint32_t rsv_0x344; /* 0x344 */
207 uint32_t mac12_clk_delay_100M; /* 0x348 */
208 uint32_t mac12_clk_delay_10M; /* 0x34C */
209 uint32_t mac34_clk_delay; /* 0x350 */
210 uint32_t rsv_0x354; /* 0x354 */
211 uint32_t mac34_clk_delay_100M; /* 0x358 */
212 uint32_t mac34_clk_delay_10M; /* 0x35C */
213 uint32_t clkduty_meas_ctrl; /* 0x360 */
214 uint32_t clkduty1; /* 0x364 */
215 uint32_t clkduty2; /* 0x368 */
216 uint32_t clkduty_meas_res; /* 0x36C */
217 uint32_t clkduty_meas_ctrl2; /* 0x370 */
218 uint32_t clkduty3; /* 0x374 */
219 uint32_t rsv_0x378[34]; /* 0x378 ~ 0x3FC */
220 uint32_t pinmux1; /* 0x400 */
221 uint32_t pinmux2; /* 0x404 */
222 uint32_t rsv_0x408; /* 0x408 */
223 uint32_t pinmux3; /* 0x40C */
224 uint32_t pinmux4; /* 0x410 */
225 uint32_t pinmux5; /* 0x414 */
226 uint32_t pinmux6; /* 0x418 */
227 uint32_t pinmux7; /* 0x41C */
228 uint32_t rsv_0x420[4]; /* 0x420 ~ 0x42C */
229 uint32_t pinmux8; /* 0x430 */
230 uint32_t pinmux9; /* 0x434 */
231 uint32_t pinmux10; /* 0x438 */
232 uint32_t rsv_0x43c; /* 0x43C */
233 uint32_t pinmux12; /* 0x440 */
234 uint32_t pinmux13; /* 0x444 */
235 uint32_t rsv_0x448[2]; /* 0x448 ~ 0x44C */
236 uint32_t pinmux14; /* 0x450 */
237 uint32_t pinmux15; /* 0x454 */
238 uint32_t pinmux16; /* 0x458 */
239 uint32_t rsv_0x45c[21]; /* 0x45C ~ 0x4AC */
240 uint32_t pinmux17; /* 0x4B0 */
241 uint32_t pinmux18; /* 0x4B4 */
242 uint32_t pinmux19; /* 0x4B8 */
243 uint32_t pinmux20; /* 0x4BC */
244 uint32_t rsv_0x4c0[5]; /* 0x4C0 ~ 0x4D0 */
245 uint32_t pinmux22; /* 0x4D4 */
246 uint32_t pinmux23; /* 0x4D8 */
247 uint32_t rsv_0x4dc[9]; /* 0x4DC ~ 0x4FC */
248 uint32_t hwstrap1; /* 0x500 */
249 uint32_t hwstrap_clr1; /* 0x504 */
250 uint32_t hwstrap_prot1; /* 0x508 */
251 uint32_t rsv_0x50c; /* 0x50C */
252 uint32_t hwstrap2; /* 0x510 */
253 uint32_t hwstrap_clr2; /* 0x514 */
254 uint32_t hwstrap_prot2; /* 0x518 */
255 uint32_t rsv_0x51c; /* 0x51C */
256 uint32_t rng_ctrl; /* 0x520 */
257 uint32_t rng_data; /* 0x524 */
258 uint32_t rsv_0x528[6]; /* 0x528 ~ 0x53C */
259 uint32_t pwr_save_wakeup_en1; /* 0x540 */
260 uint32_t pwr_save_wakeup_ctrl1; /* 0x544 */
261 uint32_t rsv_0x548[2]; /* 0x548 */
262 uint32_t pwr_save_wakeup_en2; /* 0x550 */
263 uint32_t pwr_save_wakeup_ctrl2; /* 0x554 */
264 uint32_t rsv_0x558[2]; /* 0x558 */
265 uint32_t intr1_ctrl_sts; /* 0x560 */
266 uint32_t rsv_0x564[3]; /* 0x564 */
267 uint32_t intr2_ctrl_sts; /* 0x570 */
268 uint32_t rsv_0x574[7]; /* 0x574 ~ 0x58C */
269 uint32_t otp_ctrl; /* 0x590 */
270 uint32_t efuse; /* 0x594 */
271 uint32_t rsv_0x598[6]; /* 0x598 */
272 uint32_t chip_unique_id[8]; /* 0x5B0 */
273 uint32_t rsv_0x5e0[8]; /* 0x5E0 ~ 0x5FC */
274 uint32_t disgpio_in_pull_down0; /* 0x610 */
275 uint32_t disgpio_in_pull_down1; /* 0x614 */
276 uint32_t disgpio_in_pull_down2; /* 0x618 */
277 uint32_t disgpio_in_pull_down3; /* 0x61C */
278 uint32_t rsv_0x620[4]; /* 0x620 ~ 0x62C */
279 uint32_t disgpio_in_pull_down4; /* 0x630 */
280 uint32_t disgpio_in_pull_down5; /* 0x634 */
281 uint32_t disgpio_in_pull_down6; /* 0x638 */
282 uint32_t rsv_0x63c[5]; /* 0x63C ~ 0x64C */
283 uint32_t sli_driving_strength; /* 0x650 */
284 uint32_t rsv_0x654[107]; /* 0x654 ~ 0x7FC */
285 uint32_t ca7_ctrl1; /* 0x800 */
286 uint32_t ca7_ctrl2; /* 0x804 */
287 uint32_t ca7_ctrl3; /* 0x808 */
288 uint32_t ca7_ctrl4; /* 0x80C */
289 uint32_t rsv_0x810[4]; /* 0x810 ~ 0x81C */
290 uint32_t ca7_parity_chk; /* 0x820 */
291 uint32_t ca7_parity_clr; /* 0x824 */
292 uint32_t rsv_0x828[118]; /* 0x828 ~ 0x9FC */
293 uint32_t cm3_ctrl; /* 0xA00 */
294 uint32_t cm3_base; /* 0xA04 */
295 uint32_t cm3_imem_addr; /* 0xA08 */
296 uint32_t cm3_dmem_addr; /* 0xA0C */
297 uint32_t rsv_0xa10[12]; /* 0xA10 ~ 0xA3C */
298 uint32_t cm3_cache_area; /* 0xA40 */
299 uint32_t cm3_cache_invd_ctrl; /* 0xA44 */
300 uint32_t cm3_cache_func_ctrl; /* 0xA48 */
301 uint32_t rsv_0xa4c[108]; /* 0xA4C ~ 0xBFC */
302 uint32_t pci_cfg[3]; /* 0xC00 */
303 uint32_t rsv_0xc0c[5]; /* 0xC0C ~ 0xC1C */
304 uint32_t pcie_cfg; /* 0xC20 */
305 uint32_t mmio_decode; /* 0xC24 */
306 uint32_t reloc_ctrl_decode[2]; /* 0xC28 */
307 uint32_t rsv_0xc30[4]; /* 0xC30 ~ 0xC3C */
308 uint32_t mbox_decode; /* 0xC40 */
309 uint32_t shared_sram_decode[2]; /* 0xC44 */
310 uint32_t bmc_rev_id; /* 0xC4C */
311 uint32_t rsv_0xc50[5]; /* 0xC50 ~ 0xC60 */
312 uint32_t bmc_device_id; /* 0xC64 */
313 uint32_t rsv_0xc68[102]; /* 0xC68 ~ 0xDFC */
314 uint32_t vga_scratch1; /* 0xE00 */
315 uint32_t vga_scratch2; /* 0xE04 */
316 uint32_t vga_scratch3; /* 0xE08 */
317 uint32_t vga_scratch4; /* 0xE0C */
318 uint32_t rsv_0xe10[4]; /* 0xE10 ~ 0xE1C */
319 uint32_t vga_scratch5; /* 0xE20 */
320 uint32_t vga_scratch6; /* 0xE24 */
321 uint32_t vga_scratch7; /* 0xE28 */
322 uint32_t vga_scratch8; /* 0xE2C */
323 uint32_t rsv_0xe30[52]; /* 0xE30 ~ 0xEFC */
324 uint32_t wr_prot1; /* 0xF00 */
325 uint32_t wr_prot2; /* 0xF04 */
326 uint32_t wr_prot3; /* 0xF08 */
327 uint32_t wr_prot4; /* 0xF0C */
328 uint32_t wr_prot5; /* 0xF10 */
329 uint32_t wr_prot6; /* 0xF18 */
330 uint32_t wr_prot7; /* 0xF1C */
331 uint32_t wr_prot8; /* 0xF20 */
332 uint32_t wr_prot9; /* 0xF24 */
333 uint32_t rsv_0xf28[2]; /* 0xF28 ~ 0xF2C */
334 uint32_t wr_prot10; /* 0xF30 */
335 uint32_t wr_prot11; /* 0xF34 */
336 uint32_t wr_prot12; /* 0xF38 */
337 uint32_t wr_prot13; /* 0xF3C */
338 uint32_t wr_prot14; /* 0xF40 */
339 uint32_t rsv_0xf44; /* 0xF44 */
340 uint32_t wr_prot15; /* 0xF48 */
341 uint32_t rsv_0xf4c[5]; /* 0xF4C ~ 0xF5C */
342 uint32_t wr_prot16; /* 0xF60 */
343};
344#endif
345#endif