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git01.mediatek.com / filogic / uboot / df0f95a9b87f23ff174a2a17c66659beba56f5d5 / . / arch / arm / dts / zynqmp-sc-vm-p-m1369-00-revA.dtso
blob: 8412aecd726cd9e3d93d6a2d93d0dcc6fd5ec2cc [file] [log] [blame]
Michal Simek81bab432024-09-25 09:03:38 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VM-P-M1369-00
4 *
5 * Copyright (C) 2024, Advanced Micro Devices, Inc.
6 *
7 * Michal Simek <michal.simek@amd.com>
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11
12/dts-v1/;
13/plugin/;
14
15&{/} {
16 compatible = "xlnx,zynqmp-sc-vm-p-m1369-revA",
17 "xlnx,zynqmp-sc-vm-p-m1369", "xlnx,zynqmp";
18
19 ina226-u19 {
20 compatible = "iio-hwmon";
21 io-channels = <&vcc_soc_ina 0>, <&vcc_soc_ina 1>, <&vcc_soc_ina 2>;
22 };
23 ina226-u287 {
24 compatible = "iio-hwmon";
25 io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>;
26 };
27 ina226-u288 {
28 compatible = "iio-hwmon";
29 io-channels = <&vcc_pslp_ina 0>, <&vcc_pslp_ina 1>, <&vcc_pslp_ina 2>;
30 };
31 ina226-u289 {
32 compatible = "iio-hwmon";
33 io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>;
34 };
35 ina226-u290 {
36 compatible = "iio-hwmon";
37 io-channels = <&vccaux_pmc_ina 0>, <&vccaux_pmc_ina 1>, <&vccaux_pmc_ina 2>;
38 };
39 ina226-u291 {
40 compatible = "iio-hwmon";
41 io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>;
42 };
43 ina226-u292 {
44 compatible = "iio-hwmon";
45 io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>;
46 };
47 ina226-u293 {
48 compatible = "iio-hwmon";
49 io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>;
50 };
51 ina226-u294 {
52 compatible = "iio-hwmon";
53 io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>;
54 };
55 ina226-u295 {
56 compatible = "iio-hwmon";
57 io-channels = <&vcc_ddr5_rdimm_ina 0>, <&vcc_ddr5_rdimm_ina 1>, <&vcc_ddr5_rdimm_ina 2>;
58 };
59 ina226-u298 {
60 compatible = "iio-hwmon";
61 io-channels = <&lp5_1v0_ina 0>, <&lp5_1v0_ina 1>, <&lp5_1v0_ina 2>;
62 };
63 ina226-u296 {
64 compatible = "iio-hwmon";
65 io-channels = <&vcc_fmc_ina 0>, <&vcc_fmc_ina 1>, <&vcc_fmc_ina 2>;
66 };
67 ina226-u299 {
68 compatible = "iio-hwmon";
69 io-channels = <&gtm_avcc_ina 0>, <&gtm_avcc_ina 1>, <&gtm_avcc_ina 2>;
70 };
71 ina226-u300 {
72 compatible = "iio-hwmon";
73 io-channels = <&gtm_avtt_ina 0>, <&gtm_avtt_ina 1>, <&gtm_avtt_ina 2>;
74 };
75 ina226-u301 {
76 compatible = "iio-hwmon";
77 io-channels = <&gtm_avccaux_ina 0>, <&gtm_avccaux_ina 1>, <&gtm_avccaux_ina 2>;
78 };
79 ina226-u297 {
80 compatible = "iio-hwmon";
81 io-channels = <&vcc_mipi_ina 0>, <&vcc_mipi_ina 1>, <&vcc_mipi_ina 2>;
82 };
83};
84
85&i2c1 { /* i2c_main bus */
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */
90
91 /* i2c_main_1 - u72 - j108 - disable translation, add 8 */
92 /* J133 - OE for u91@55 + 8 - 161,132813MHz - QSFP56G_0 */
93 qsfp56g_0_clk: clock-controller@5d {
94 compatible = "renesas,proxo-xp";
95 reg = <0x5d>;
96 #clock-cells = <0>;
97 clock-output-names = "qsfp56g_0_clk";
98 };
99
100 /* J134 - OE for u92@57 + 8 - 322,265625MHz - QSFP56G_1 */
101 qsfp56g_1_clk: clock-controller@5f {
102 compatible = "renesas,proxo-xp";
103 reg = <0x5f>;
104 #clock-cells = <0>;
105 clock-output-names = "qsfp56g_1_clk";
106 };
107
108 /* i2c_main_2 - u74 - j110 - disable translation, add 9 */
109 /* J210 - OE for u164@50 + 9 - 320MHz - CH2_LP5 */
110 ch2_lpddr5_refclk: clock-controller@59 {
111 compatible = "renesas,proxo-xp";
112 reg = <0x59>;
113 #clock-cells = <0>;
114 clock-output-names = "ch2_lpddr5_refclk";
115 };
116
117 /* i2c_main_3 - u76 - j112 - disable translation, add 6 */
118 /* J231 - OE for u165@50 + 6 - 320MHz - _RDIMM */
119 ddr5_dimm1_refclk: clock-controller@56 {
120 compatible = "renesas,proxo-xp";
121 reg = <0x56>;
122 #clock-cells = <0>;
123 clock-output-names = "ddr5_udimm_refclk";
124 };
125
126 /* i2c_main_4 - u73 - j109 - disable translation, add 5 */
127 /* J117 - OE for u82@50 + 5 - 33,3333MHz - PS_REFCLK */
128 ps_refclk: clock-controller@55 {
129 compatible = "renesas,proxo-xp";
130 reg = <0x55>;
131 #clock-cells = <0>;
132 clock-output-names = "ps_refclk";
133 };
134
135 /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */
136 /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */
137 /* this should be SW controlable too */
138};
139
140&i2c0 {
141 #address-cells = <1>;
142 #size-cells = <0>;
143
144 /* u134 tps544b25 but connected to J178 connector */
145 /* u48/IMx3112/0x77 - 1:2 multiplexer - also accessed from Versal NET */
146 /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */
147 /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */
148 /* Access to i2c_pmc bus via u49 with OE j100 or via SYSCTLR_I2C_PMC_EN */
149
150 /* ina226_pmbus - J103 - disable INA226_PMBUS */
151 vcc_soc_ina: power-monitor@40 { /* u19 */
152 compatible = "ti,ina226";
153 #io-channel-cells = <1>;
154 reg = <0x40>;
155 shunt-resistor = <1000>; /* R222 */
156 };
157
158 vcc_ram_ina: power-monitor@41 { /* u287 */
159 compatible = "ti,ina226";
160 #io-channel-cells = <1>;
161 reg = <0x41>;
162 shunt-resistor = <1000>; /* R32981 */
163 };
164
165 vcc_pslp_ina: power-monitor@42 { /* u288 */
166 compatible = "ti,ina226";
167 #io-channel-cells = <1>;
168 reg = <0x42>;
169 shunt-resistor = <1000>; /* R32984 */
170 };
171
172 vccaux_ina: power-monitor@43 { /* u289 */
173 compatible = "ti,ina226";
174 #io-channel-cells = <1>;
175 reg = <0x43>;
176 shunt-resistor = <1000>; /* R32987 */
177 };
178
179 vccaux_pmc_ina: power-monitor@44 { /* u290 */
180 compatible = "ti,ina226";
181 #io-channel-cells = <1>;
182 reg = <0x44>;
183 shunt-resistor = <1000>; /* R32990 */
184 };
185
186 vcco_500_ina: power-monitor@45 { /* u291 */
187 compatible = "ti,ina226";
188 #io-channel-cells = <1>;
189 reg = <0x45>;
190 shunt-resistor = <1000>; /* R32993 */
191 };
192
193 vcco_501_ina: power-monitor@46 { /* u292 */
194 compatible = "ti,ina226";
195 #io-channel-cells = <1>;
196 reg = <0x46>;
197 shunt-resistor = <1000>; /* R32996 */
198 };
199
200 vcco_502_ina: power-monitor@47 { /* u293 */
201 compatible = "ti,ina226";
202 #io-channel-cells = <1>;
203 reg = <0x47>;
204 shunt-resistor = <1000>; /* R32999 */
205 };
206
207 vcco_503_ina: power-monitor@48 { /* u294 */
208 compatible = "ti,ina226";
209 #io-channel-cells = <1>;
210 reg = <0x48>;
211 shunt-resistor = <1000>; /* R33002 */
212 };
213
214 vcc_ddr5_rdimm_ina: power-monitor@49 { /* u295 */
215 compatible = "ti,ina226";
216 #io-channel-cells = <1>;
217 reg = <0x49>;
218 shunt-resistor = <1000>; /* R33005 */
219 };
220
221 lp5_1v0_ina: power-monitor@4a { /* u298 */
222 compatible = "ti,ina226";
223 #io-channel-cells = <1>;
224 reg = <0x4a>;
225 shunt-resistor = <1000>; /* R33014 */
226 };
227
228 vcc_fmc_ina: power-monitor@4b { /* u296 */
229 compatible = "ti,ina226";
230 #io-channel-cells = <1>;
231 reg = <0x4b>;
232 shunt-resistor = <1000>; /* R33008 */
233 };
234
235 gtm_avcc_ina: power-monitor@4c { /* u299 */
236 compatible = "ti,ina226";
237 #io-channel-cells = <1>;
238 reg = <0x4c>;
239 shunt-resistor = <1000>; /* R33017 */
240 };
241
242 gtm_avtt_ina: power-monitor@4d { /* u300 */
243 compatible = "ti,ina226";
244 #io-channel-cells = <1>;
245 reg = <0x4d>;
246 shunt-resistor = <1000>; /* R33020 */
247 };
248
249 gtm_avccaux_ina: power-monitor@4e { /* u301 */
250 compatible = "ti,ina226";
251 #io-channel-cells = <1>;
252 reg = <0x4e>;
253 shunt-resistor = <1000>; /* R33023 */
254 };
255
256 vcc_mipi_ina: power-monitor@4f { /* u297 */
257 compatible = "ti,ina226";
258 #io-channel-cells = <1>;
259 reg = <0x4f>;
260 shunt-resistor = <1000>; /* R33011 */
261 };
262
263 /* pmbus - j105 - disable main PMBUS - also going to j102 connector */
264 vcc_pslp: regulator@15 { /* u24 */
265 compatible = "ti,tps546b24a";
266 reg = <0x15>;
267 };
268
269 vccaux_pmc: regulator@17 { /* u26 */
270 compatible = "ti,tps546b24a";
271 reg = <0x17>;
272 };
273
274 vcco_500: regulator@18 { /* u27 */
275 compatible = "ti,tps546b24a";
276 reg = <0x18>;
277 };
278
279 vcco_501: regulator@19 { /* u28 */
280 compatible = "ti,tps546b24a";
281 reg = <0x19>;
282 };
283
284 vcco_502: regulator@1a { /* u29 */
285 compatible = "ti,tps546b24a";
286 reg = <0x1a>;
287 };
288
289 vcco_503: regulator@1b { /* u30 */
290 compatible = "ti,tps546b24a";
291 reg = <0x1b>;
292 };
293
294 vcc_ddr5_rdimm: regulator@1c { /* u31 */
295 compatible = "ti,tps546b24a";
296 reg = <0x1c>;
297 };
298
299 gtm_avcc: regulator@22 { /* u37 */
300 compatible = "ti,tps546b24a";
301 reg = <0x22>;
302 };
303
304 gtm_avtt: regulator@20 { /* u38 */
305 compatible = "ti,tps546b24a";
306 reg = <0x20>;
307 };
308
309 gtm_avccaux: regulator@21 { /* u39 */
310 compatible = "ti,tps546b24a";
311 reg = <0x21>;
312 };
313
314 vccint_gt: regulator@2a { /* u44 */
315 compatible = "ti,tps546b24a";
316 reg = <0x2a>;
317 };
318
319 util_1v8: regulator@2b { /* u1839 */
320 compatible = "ti,tps546b24a";
321 reg = <0x2b>;
322 };
323
324 vcc_pmc: regulator@2c { /* u46 */
325 compatible = "ti,tps546b24a";
326 reg = <0x2c>;
327 };
328
329 /* pmbus via U62 as ext_pmbus - disable via j104 */
330 vccint: regulator@10 { /* u18 */
331 compatible = "ti,tps546b24";
332 reg = <0x10>;
333 };
334
335 vccsoc: regulator@11 { /* u20 */
336 compatible = "ti,tps546b24";
337 reg = <0x11>;
338 };
339
340 vcc_io: regulator@12 { /* u21 */
341 compatible = "ti,tps546b24";
342 reg = <0x12>;
343 };
344
345 vcc_psfp: regulator@13 { /* u22 */
346 compatible = "ti,tps546b24";
347 reg = <0x13>;
348 };
349
350 vcc_ram: regulator@14 { /* u23 */
351 compatible = "ti,tps546b24";
352 reg = <0x14>;
353 };
354
355 vccaux: regulator@16 { /* u25 */
356 compatible = "ti,tps546b24";
357 reg = <0x16>;
358 };
359
360 lp5_1v0: regulator@1d { /* u32 */
361 compatible = "ti,tps546b24";
362 reg = <0x1d>;
363 };
364
365 vcc_fmc: regulator@1e { /* u33 */
366 compatible = "ti,tps546b24";
367 reg = <0x1e>;
368 };
369
370 lp5_vdd1: regulator@25 { /* u40 */
371 compatible = "ti,tps546b24";
372 reg = <0x25>;
373 };
374
375 lp5_vdd2: regulator@26 { /* u41 */
376 compatible = "ti,tps546b24";
377 reg = <0x26>;
378 };
379
380 lp5_vddq: regulator@27 { /* u42 */
381 compatible = "ti,tps546b24";
382 reg = <0x27>;
383 };
384
385 vcco_hdio: regulator@29 { /* u43 */
386 compatible = "ti,tps546b24";
387 reg = <0x29>;
388 };
389
390 vcc_mipi: regulator@1f { /* u47 */
391 compatible = "ti,tps546b24";
392 reg = <0x1f>;
393 };
394
395 /* connected via J425 connector
396 ucd90320: power-sequencer@73 { // u16
397 compatible = "ti,ucd90320";
398 reg = <0x73>;
399 };*/
400};