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Michal Simek0dd222b2013-04-22 14:56:49 +02001/*
Michal Simek9ecd2682015-11-30 16:13:03 +01002 * (C) Copyright 2013 - 2015 Xilinx, Inc.
Michal Simek0dd222b2013-04-22 14:56:49 +02003 *
4 * Xilinx Zynq SD Host Controller Interface
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Michal Simek0dd222b2013-04-22 14:56:49 +02007 */
8
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +01009#include <clk.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020010#include <common.h>
Michal Simek9ecd2682015-11-30 16:13:03 +010011#include <dm.h>
Michal Simekc57ba042014-02-24 11:16:31 +010012#include <fdtdec.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090013#include <linux/libfdt.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020014#include <malloc.h>
15#include <sdhci.h>
Michal Simek0dd222b2013-04-22 14:56:49 +020016
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +010017DECLARE_GLOBAL_DATA_PTR;
18
Simon Glass4cc87fb2016-07-05 17:10:15 -060019struct arasan_sdhci_plat {
20 struct mmc_config cfg;
21 struct mmc mmc;
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +010022 unsigned int f_max;
Simon Glass4cc87fb2016-07-05 17:10:15 -060023};
24
Michal Simek9ecd2682015-11-30 16:13:03 +010025static int arasan_sdhci_probe(struct udevice *dev)
Michal Simek0dd222b2013-04-22 14:56:49 +020026{
Simon Glass4cc87fb2016-07-05 17:10:15 -060027 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Michal Simek9ecd2682015-11-30 16:13:03 +010028 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
29 struct sdhci_host *host = dev_get_priv(dev);
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +010030 struct clk clk;
31 unsigned long clock;
Simon Glass4cc87fb2016-07-05 17:10:15 -060032 int ret;
Michal Simek0dd222b2013-04-22 14:56:49 +020033
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +010034 ret = clk_get_by_index(dev, 0, &clk);
35 if (ret < 0) {
36 dev_err(dev, "failed to get clock\n");
37 return ret;
38 }
39
40 clock = clk_get_rate(&clk);
41 if (IS_ERR_VALUE(clock)) {
42 dev_err(dev, "failed to get rate\n");
43 return clock;
44 }
45 debug("%s: CLK %ld\n", __func__, clock);
46
47 ret = clk_enable(&clk);
48 if (ret && ret != -ENOSYS) {
49 dev_err(dev, "failed to enable clock\n");
50 return ret;
51 }
52
Siva Durga Prasad Paladugu049e0032014-07-08 15:31:04 +053053 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
Siva Durga Prasad Paladugu0d6891b2014-01-22 09:17:09 +010054 SDHCI_QUIRK_BROKEN_R1B;
Siva Durga Prasad Paladugua1619fe2016-01-12 15:12:16 +053055
56#ifdef CONFIG_ZYNQ_HISPD_BROKEN
57 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
58#endif
59
Stefan Herbrechtsmeier739ae402017-01-17 16:27:32 +010060 host->max_clk = clock;
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +010061
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +010062 ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +090063 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
Simon Glass4cc87fb2016-07-05 17:10:15 -060064 host->mmc = &plat->mmc;
65 if (ret)
66 return ret;
67 host->mmc->priv = host;
Simon Glass77ca42b2016-05-01 13:52:34 -060068 host->mmc->dev = dev;
Simon Glass4cc87fb2016-07-05 17:10:15 -060069 upriv->mmc = host->mmc;
Michal Simek9ecd2682015-11-30 16:13:03 +010070
Simon Glass4cc87fb2016-07-05 17:10:15 -060071 return sdhci_probe(dev);
Michal Simek0dd222b2013-04-22 14:56:49 +020072}
Michal Simek9ecd2682015-11-30 16:13:03 +010073
74static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
75{
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +010076 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Michal Simek9ecd2682015-11-30 16:13:03 +010077 struct sdhci_host *host = dev_get_priv(dev);
78
Masahiro Yamadaa4405612016-04-22 20:59:31 +090079 host->name = dev->name;
Simon Glassba1dea42017-05-17 17:18:05 -060080 host->ioaddr = (void *)devfdt_get_addr(dev);
Michal Simek9ecd2682015-11-30 16:13:03 +010081
Simon Glass7a494432017-05-17 17:18:09 -060082 plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Stefan Herbrechtsmeier5567b422017-01-17 16:27:33 +010083 "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
84
Michal Simek9ecd2682015-11-30 16:13:03 +010085 return 0;
86}
87
Simon Glass4cc87fb2016-07-05 17:10:15 -060088static int arasan_sdhci_bind(struct udevice *dev)
89{
90 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Simon Glass4cc87fb2016-07-05 17:10:15 -060091
Masahiro Yamadacdb67f32016-09-06 22:17:32 +090092 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glass4cc87fb2016-07-05 17:10:15 -060093}
94
Michal Simek9ecd2682015-11-30 16:13:03 +010095static const struct udevice_id arasan_sdhci_ids[] = {
96 { .compatible = "arasan,sdhci-8.9a" },
97 { }
98};
99
100U_BOOT_DRIVER(arasan_sdhci_drv) = {
101 .name = "arasan_sdhci",
102 .id = UCLASS_MMC,
103 .of_match = arasan_sdhci_ids,
104 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
Simon Glass4cc87fb2016-07-05 17:10:15 -0600105 .ops = &sdhci_ops,
106 .bind = arasan_sdhci_bind,
Michal Simek9ecd2682015-11-30 16:13:03 +0100107 .probe = arasan_sdhci_probe,
108 .priv_auto_alloc_size = sizeof(struct sdhci_host),
Simon Glass4cc87fb2016-07-05 17:10:15 -0600109 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
Michal Simek9ecd2682015-11-30 16:13:03 +0100110};