Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 1 | /* |
Allen Martin | 55d98a1 | 2012-08-31 08:30:00 +0000 | [diff] [blame] | 2 | * NVIDIA Tegra20 GPIO handling. |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 3 | * (C) Copyright 2010-2012,2015 |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 4 | * NVIDIA Corporation <www.nvidia.com> |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver. |
| 11 | * Tom Warren (twarren@nvidia.com) |
| 12 | */ |
| 13 | |
| 14 | #include <common.h> |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 15 | #include <dm.h> |
| 16 | #include <malloc.h> |
| 17 | #include <errno.h> |
| 18 | #include <fdtdec.h> |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 19 | #include <asm/io.h> |
| 20 | #include <asm/bitops.h> |
Tom Warren | ab37196 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 21 | #include <asm/arch/tegra.h> |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 22 | #include <asm/gpio.h> |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 23 | #include <dm/device-internal.h> |
Simon Glass | ada3b75 | 2015-01-05 20:05:33 -0700 | [diff] [blame] | 24 | #include <dt-bindings/gpio/gpio.h> |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 25 | |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 26 | static const int CONFIG_SFIO = 0; |
| 27 | static const int CONFIG_GPIO = 1; |
| 28 | static const int DIRECTION_INPUT = 0; |
| 29 | static const int DIRECTION_OUTPUT = 1; |
| 30 | |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 31 | struct tegra_gpio_platdata { |
| 32 | struct gpio_ctlr_bank *bank; |
| 33 | const char *port_name; /* Name of port, e.g. "B" */ |
| 34 | int base_gpio; /* Port number for this port (0, 1,.., n-1) */ |
| 35 | }; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 36 | |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 37 | /* Information about each port at run-time */ |
| 38 | struct tegra_port_info { |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 39 | struct gpio_ctlr_bank *bank; |
| 40 | int base_gpio; /* Port number for this port (0, 1,.., n-1) */ |
| 41 | }; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 42 | |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 43 | /* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */ |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 44 | static int get_config(unsigned gpio) |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 45 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 46 | struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; |
| 47 | struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 48 | u32 u; |
| 49 | int type; |
| 50 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 51 | u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 52 | type = (u >> GPIO_BIT(gpio)) & 1; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 53 | |
| 54 | debug("get_config: port = %d, bit = %d is %s\n", |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 55 | GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 56 | |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 57 | return type ? CONFIG_GPIO : CONFIG_SFIO; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 58 | } |
| 59 | |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 60 | /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */ |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 61 | static void set_config(unsigned gpio, int type) |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 62 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 63 | struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; |
| 64 | struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 65 | u32 u; |
| 66 | |
| 67 | debug("set_config: port = %d, bit = %d, %s\n", |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 68 | GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 69 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 70 | u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 71 | if (type != CONFIG_SFIO) |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 72 | u |= 1 << GPIO_BIT(gpio); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 73 | else |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 74 | u &= ~(1 << GPIO_BIT(gpio)); |
| 75 | writel(u, &bank->gpio_config[GPIO_PORT(gpio)]); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 76 | } |
| 77 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 78 | /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */ |
| 79 | static int get_direction(unsigned gpio) |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 80 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 81 | struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; |
| 82 | struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 83 | u32 u; |
| 84 | int dir; |
| 85 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 86 | u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); |
| 87 | dir = (u >> GPIO_BIT(gpio)) & 1; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 88 | |
| 89 | debug("get_direction: port = %d, bit = %d, %s\n", |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 90 | GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 91 | |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 92 | return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 93 | } |
| 94 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 95 | /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ |
| 96 | static void set_direction(unsigned gpio, int output) |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 97 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 98 | struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; |
| 99 | struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 100 | u32 u; |
| 101 | |
| 102 | debug("set_direction: port = %d, bit = %d, %s\n", |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 103 | GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 104 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 105 | u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 106 | if (output != DIRECTION_INPUT) |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 107 | u |= 1 << GPIO_BIT(gpio); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 108 | else |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 109 | u &= ~(1 << GPIO_BIT(gpio)); |
| 110 | writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 111 | } |
| 112 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 113 | /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */ |
| 114 | static void set_level(unsigned gpio, int high) |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 115 | { |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 116 | struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; |
| 117 | struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 118 | u32 u; |
| 119 | |
| 120 | debug("set_level: port = %d, bit %d == %d\n", |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 121 | GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 122 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 123 | u = readl(&bank->gpio_out[GPIO_PORT(gpio)]); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 124 | if (high) |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 125 | u |= 1 << GPIO_BIT(gpio); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 126 | else |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 127 | u &= ~(1 << GPIO_BIT(gpio)); |
| 128 | writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | /* |
| 132 | * Generic_GPIO primitives. |
| 133 | */ |
| 134 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 135 | /* set GPIO pin 'gpio' as an input */ |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 136 | static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 137 | { |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 138 | struct tegra_port_info *state = dev_get_priv(dev); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 139 | |
| 140 | /* Configure GPIO direction as input. */ |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 141 | set_direction(state->base_gpio + offset, DIRECTION_INPUT); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 142 | |
Stephen Warren | 6904f6d | 2015-09-23 12:13:00 -0600 | [diff] [blame] | 143 | /* Enable the pin as a GPIO */ |
| 144 | set_config(state->base_gpio + offset, 1); |
| 145 | |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 146 | return 0; |
| 147 | } |
| 148 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 149 | /* set GPIO pin 'gpio' as an output, with polarity 'value' */ |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 150 | static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset, |
| 151 | int value) |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 152 | { |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 153 | struct tegra_port_info *state = dev_get_priv(dev); |
| 154 | int gpio = state->base_gpio + offset; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 155 | |
| 156 | /* Configure GPIO output value. */ |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 157 | set_level(gpio, value); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 158 | |
| 159 | /* Configure GPIO direction as output. */ |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 160 | set_direction(gpio, DIRECTION_OUTPUT); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 161 | |
Stephen Warren | 6904f6d | 2015-09-23 12:13:00 -0600 | [diff] [blame] | 162 | /* Enable the pin as a GPIO */ |
| 163 | set_config(state->base_gpio + offset, 1); |
| 164 | |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 165 | return 0; |
| 166 | } |
| 167 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 168 | /* read GPIO IN value of pin 'gpio' */ |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 169 | static int tegra_gpio_get_value(struct udevice *dev, unsigned offset) |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 170 | { |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 171 | struct tegra_port_info *state = dev_get_priv(dev); |
| 172 | int gpio = state->base_gpio + offset; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 173 | int val; |
| 174 | |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 175 | debug("%s: pin = %d (port %d:bit %d)\n", __func__, |
| 176 | gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); |
| 177 | |
Simon Glass | 5f4de1f | 2016-01-30 16:37:45 -0700 | [diff] [blame] | 178 | if (get_direction(gpio) == DIRECTION_INPUT) |
| 179 | val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]); |
| 180 | else |
| 181 | val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 182 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 183 | return (val >> GPIO_BIT(gpio)) & 1; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 184 | } |
| 185 | |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 186 | /* write GPIO OUT value to pin 'gpio' */ |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 187 | static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value) |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 188 | { |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 189 | struct tegra_port_info *state = dev_get_priv(dev); |
| 190 | int gpio = state->base_gpio + offset; |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 191 | |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 192 | debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 193 | gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 194 | |
| 195 | /* Configure GPIO output value. */ |
Joe Hershberger | f8928f1 | 2011-11-11 15:55:36 -0600 | [diff] [blame] | 196 | set_level(gpio, value); |
| 197 | |
| 198 | return 0; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 199 | } |
| 200 | |
Stephen Warren | 4b27bf1 | 2014-04-22 14:37:53 -0600 | [diff] [blame] | 201 | void gpio_config_table(const struct tegra_gpio_config *config, int len) |
| 202 | { |
| 203 | int i; |
| 204 | |
| 205 | for (i = 0; i < len; i++) { |
| 206 | switch (config[i].init) { |
| 207 | case TEGRA_GPIO_INIT_IN: |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 208 | set_direction(config[i].gpio, DIRECTION_INPUT); |
Stephen Warren | 4b27bf1 | 2014-04-22 14:37:53 -0600 | [diff] [blame] | 209 | break; |
| 210 | case TEGRA_GPIO_INIT_OUT0: |
Stephen Warren | c6f5402 | 2015-09-23 12:12:59 -0600 | [diff] [blame] | 211 | set_level(config[i].gpio, 0); |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 212 | set_direction(config[i].gpio, DIRECTION_OUTPUT); |
Stephen Warren | 4b27bf1 | 2014-04-22 14:37:53 -0600 | [diff] [blame] | 213 | break; |
| 214 | case TEGRA_GPIO_INIT_OUT1: |
Stephen Warren | c6f5402 | 2015-09-23 12:12:59 -0600 | [diff] [blame] | 215 | set_level(config[i].gpio, 1); |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 216 | set_direction(config[i].gpio, DIRECTION_OUTPUT); |
Stephen Warren | 4b27bf1 | 2014-04-22 14:37:53 -0600 | [diff] [blame] | 217 | break; |
| 218 | } |
Stephen Warren | 20a9145 | 2015-09-25 10:44:08 -0600 | [diff] [blame] | 219 | set_config(config[i].gpio, CONFIG_GPIO); |
Stephen Warren | 4b27bf1 | 2014-04-22 14:37:53 -0600 | [diff] [blame] | 220 | } |
| 221 | } |
| 222 | |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 223 | static int tegra_gpio_get_function(struct udevice *dev, unsigned offset) |
| 224 | { |
| 225 | struct tegra_port_info *state = dev_get_priv(dev); |
| 226 | int gpio = state->base_gpio + offset; |
| 227 | |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 228 | if (!get_config(gpio)) |
| 229 | return GPIOF_FUNC; |
| 230 | else if (get_direction(gpio)) |
| 231 | return GPIOF_OUTPUT; |
| 232 | else |
| 233 | return GPIOF_INPUT; |
| 234 | } |
| 235 | |
Simon Glass | ada3b75 | 2015-01-05 20:05:33 -0700 | [diff] [blame] | 236 | static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, |
Simon Glass | 12faa02 | 2017-05-18 20:09:18 -0600 | [diff] [blame] | 237 | struct ofnode_phandle_args *args) |
Simon Glass | ada3b75 | 2015-01-05 20:05:33 -0700 | [diff] [blame] | 238 | { |
| 239 | int gpio, port, ret; |
| 240 | |
| 241 | gpio = args->args[0]; |
| 242 | port = gpio / TEGRA_GPIOS_PER_PORT; |
| 243 | ret = device_get_child(dev, port, &desc->dev); |
| 244 | if (ret) |
| 245 | return ret; |
| 246 | desc->offset = gpio % TEGRA_GPIOS_PER_PORT; |
| 247 | desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; |
| 248 | |
| 249 | return 0; |
| 250 | } |
| 251 | |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 252 | static const struct dm_gpio_ops gpio_tegra_ops = { |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 253 | .direction_input = tegra_gpio_direction_input, |
| 254 | .direction_output = tegra_gpio_direction_output, |
| 255 | .get_value = tegra_gpio_get_value, |
| 256 | .set_value = tegra_gpio_set_value, |
| 257 | .get_function = tegra_gpio_get_function, |
Simon Glass | ada3b75 | 2015-01-05 20:05:33 -0700 | [diff] [blame] | 258 | .xlate = tegra_gpio_xlate, |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 259 | }; |
| 260 | |
| 261 | /** |
| 262 | * Returns the name of a GPIO port |
| 263 | * |
| 264 | * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ... |
| 265 | * |
| 266 | * @base_port: Base port number (0, 1..n-1) |
| 267 | * @return allocated string containing the name |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 268 | */ |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 269 | static char *gpio_port_name(int base_port) |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 270 | { |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 271 | char *name, *s; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 272 | |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 273 | name = malloc(3); |
| 274 | if (name) { |
| 275 | s = name; |
| 276 | *s++ = 'A' + (base_port % 26); |
| 277 | if (base_port >= 26) |
| 278 | *s++ = *name; |
| 279 | *s = '\0'; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 280 | } |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 281 | |
| 282 | return name; |
Tom Warren | b3878b8 | 2011-06-17 06:27:28 +0000 | [diff] [blame] | 283 | } |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 284 | |
| 285 | static const struct udevice_id tegra_gpio_ids[] = { |
| 286 | { .compatible = "nvidia,tegra30-gpio" }, |
| 287 | { .compatible = "nvidia,tegra20-gpio" }, |
| 288 | { } |
| 289 | }; |
| 290 | |
| 291 | static int gpio_tegra_probe(struct udevice *dev) |
| 292 | { |
Simon Glass | de0977b | 2015-03-05 12:25:20 -0700 | [diff] [blame] | 293 | struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 294 | struct tegra_port_info *priv = dev->priv; |
| 295 | struct tegra_gpio_platdata *plat = dev->platdata; |
| 296 | |
| 297 | /* Only child devices have ports */ |
| 298 | if (!plat) |
| 299 | return 0; |
| 300 | |
| 301 | priv->bank = plat->bank; |
| 302 | priv->base_gpio = plat->base_gpio; |
| 303 | |
| 304 | uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT; |
| 305 | uc_priv->bank_name = plat->port_name; |
| 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | /** |
| 311 | * We have a top-level GPIO device with no actual GPIOs. It has a child |
| 312 | * device for each Tegra port. |
| 313 | */ |
| 314 | static int gpio_tegra_bind(struct udevice *parent) |
| 315 | { |
| 316 | struct tegra_gpio_platdata *plat = parent->platdata; |
| 317 | struct gpio_ctlr *ctlr; |
| 318 | int bank_count; |
| 319 | int bank; |
| 320 | int ret; |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 321 | |
| 322 | /* If this is a child device, there is nothing to do here */ |
| 323 | if (plat) |
| 324 | return 0; |
| 325 | |
Simon Glass | e3e5a9f | 2015-03-03 08:02:59 -0700 | [diff] [blame] | 326 | /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ |
| 327 | #ifdef CONFIG_SPL_BUILD |
| 328 | ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; |
| 329 | bank_count = TEGRA_GPIO_BANKS; |
| 330 | #else |
| 331 | { |
| 332 | int len; |
| 333 | |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 334 | /* |
| 335 | * This driver does not make use of interrupts, other than to figure |
| 336 | * out the number of GPIO banks |
| 337 | */ |
Simon Glass | b0ca849 | 2017-07-25 08:30:03 -0600 | [diff] [blame] | 338 | len = dev_read_size(parent, "interrupts"); |
| 339 | if (len < 0) |
| 340 | return len; |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 341 | bank_count = len / 3 / sizeof(u32); |
Simon Glass | b0ca849 | 2017-07-25 08:30:03 -0600 | [diff] [blame] | 342 | ctlr = (struct gpio_ctlr *)dev_read_addr(parent); |
| 343 | if ((ulong)ctlr == FDT_ADDR_T_NONE) |
| 344 | return -EINVAL; |
Simon Glass | e3e5a9f | 2015-03-03 08:02:59 -0700 | [diff] [blame] | 345 | } |
| 346 | #endif |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 347 | for (bank = 0; bank < bank_count; bank++) { |
| 348 | int port; |
| 349 | |
| 350 | for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) { |
| 351 | struct tegra_gpio_platdata *plat; |
| 352 | struct udevice *dev; |
| 353 | int base_port; |
| 354 | |
| 355 | plat = calloc(1, sizeof(*plat)); |
| 356 | if (!plat) |
| 357 | return -ENOMEM; |
| 358 | plat->bank = &ctlr->gpio_bank[bank]; |
| 359 | base_port = bank * TEGRA_PORTS_PER_BANK + port; |
| 360 | plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port; |
| 361 | plat->port_name = gpio_port_name(base_port); |
| 362 | |
| 363 | ret = device_bind(parent, parent->driver, |
| 364 | plat->port_name, plat, -1, &dev); |
| 365 | if (ret) |
| 366 | return ret; |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 367 | dev_set_of_offset(dev, dev_of_offset(parent)); |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 368 | } |
| 369 | } |
| 370 | |
| 371 | return 0; |
| 372 | } |
| 373 | |
| 374 | U_BOOT_DRIVER(gpio_tegra) = { |
| 375 | .name = "gpio_tegra", |
| 376 | .id = UCLASS_GPIO, |
| 377 | .of_match = tegra_gpio_ids, |
| 378 | .bind = gpio_tegra_bind, |
| 379 | .probe = gpio_tegra_probe, |
| 380 | .priv_auto_alloc_size = sizeof(struct tegra_port_info), |
| 381 | .ops = &gpio_tegra_ops, |
Simon Glass | e3e5a9f | 2015-03-03 08:02:59 -0700 | [diff] [blame] | 382 | .flags = DM_FLAG_PRE_RELOC, |
Simon Glass | b046104 | 2014-09-03 17:37:03 -0600 | [diff] [blame] | 383 | }; |