blob: 2419636c5f5d9fccb0a9daa856587cbb3901cd42 [file] [log] [blame]
Simon Glass8fa4d5a2015-08-30 16:55:27 -06001/*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * (C) Copyright 2008-2014 Rockchip Electronics
5 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <dm.h>
Simon Glass9c73e742016-01-21 19:44:09 -070012#include <syscon.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090013#include <linux/errno.h>
Simon Glass8fa4d5a2015-08-30 16:55:27 -060014#include <asm/gpio.h>
15#include <asm/io.h>
Simon Glass9c73e742016-01-21 19:44:09 -070016#include <asm/arch/clock.h>
17#include <dm/pinctrl.h>
Simon Glass9c73e742016-01-21 19:44:09 -070018#include <dt-bindings/clock/rk3288-cru.h>
Simon Glass8fa4d5a2015-08-30 16:55:27 -060019
20enum {
21 ROCKCHIP_GPIOS_PER_BANK = 32,
22};
23
24#define OFFSET_TO_BIT(bit) (1UL << (bit))
25
26struct rockchip_gpio_priv {
27 struct rockchip_gpio_regs *regs;
Simon Glass9c73e742016-01-21 19:44:09 -070028 struct udevice *pinctrl;
29 int bank;
Simon Glass8fa4d5a2015-08-30 16:55:27 -060030 char name[2];
31};
32
33static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
34{
35 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
36 struct rockchip_gpio_regs *regs = priv->regs;
37
38 clrbits_le32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
39
40 return 0;
41}
42
43static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
44 int value)
45{
46 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
47 struct rockchip_gpio_regs *regs = priv->regs;
48 int mask = OFFSET_TO_BIT(offset);
49
50 clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
51 setbits_le32(&regs->swport_ddr, mask);
52
53 return 0;
54}
55
56static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
57{
58 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
59 struct rockchip_gpio_regs *regs = priv->regs;
60
Simon Glassc8d72402016-01-21 19:44:08 -070061 return readl(&regs->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0;
Simon Glass8fa4d5a2015-08-30 16:55:27 -060062}
63
64static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
65 int value)
66{
67 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
68 struct rockchip_gpio_regs *regs = priv->regs;
69 int mask = OFFSET_TO_BIT(offset);
70
71 clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
72
73 return 0;
74}
75
76static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
77{
Simon Glass9c73e742016-01-21 19:44:09 -070078#ifdef CONFIG_SPL_BUILD
79 return -ENODATA;
80#else
81 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
82 struct rockchip_gpio_regs *regs = priv->regs;
83 bool is_output;
84 int ret;
85
86 ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
87 if (ret)
88 return ret;
Simon Glass9c73e742016-01-21 19:44:09 -070089 is_output = readl(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
90
91 return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
92#endif
Simon Glass8fa4d5a2015-08-30 16:55:27 -060093}
94
Simon Glass8fa4d5a2015-08-30 16:55:27 -060095static int rockchip_gpio_probe(struct udevice *dev)
96{
97 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
98 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
99 char *end;
Simon Glass9c73e742016-01-21 19:44:09 -0700100 int ret;
Simon Glass8fa4d5a2015-08-30 16:55:27 -0600101
Philipp Tomsich66482052017-09-11 22:04:24 +0200102 priv->regs = dev_read_addr_ptr(dev);
Simon Glassc7298e72016-02-11 13:23:26 -0700103 ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
Simon Glass9c73e742016-01-21 19:44:09 -0700104 if (ret)
105 return ret;
Simon Glass9c73e742016-01-21 19:44:09 -0700106
Simon Glass8fa4d5a2015-08-30 16:55:27 -0600107 uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
108 end = strrchr(dev->name, '@');
Simon Glass9c73e742016-01-21 19:44:09 -0700109 priv->bank = trailing_strtoln(dev->name, end);
110 priv->name[0] = 'A' + priv->bank;
Simon Glass8fa4d5a2015-08-30 16:55:27 -0600111 uc_priv->bank_name = priv->name;
112
113 return 0;
114}
115
116static const struct dm_gpio_ops gpio_rockchip_ops = {
117 .direction_input = rockchip_gpio_direction_input,
118 .direction_output = rockchip_gpio_direction_output,
119 .get_value = rockchip_gpio_get_value,
120 .set_value = rockchip_gpio_set_value,
121 .get_function = rockchip_gpio_get_function,
Simon Glass8fa4d5a2015-08-30 16:55:27 -0600122};
123
124static const struct udevice_id rockchip_gpio_ids[] = {
125 { .compatible = "rockchip,gpio-bank" },
126 { }
127};
128
129U_BOOT_DRIVER(gpio_rockchip) = {
130 .name = "gpio_rockchip",
131 .id = UCLASS_GPIO,
132 .of_match = rockchip_gpio_ids,
133 .ops = &gpio_rockchip_ops,
134 .priv_auto_alloc_size = sizeof(struct rockchip_gpio_priv),
135 .probe = rockchip_gpio_probe,
136};