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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala38449a42009-09-10 03:02:13 -05002/*
Haiying Wang325a12f2011-01-20 22:26:31 +00003 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala38449a42009-09-10 03:02:13 -05004 */
5
6#ifndef _FSL_LIODN_H_
7#define _FSL_LIODN_H_
8
Tom Rinidee15a92024-04-30 20:40:48 -06009#include <config.h>
10#include <linux/types.h>
11#include <asm/ppc.h>
Ahmed Mansouraa270b42017-12-15 16:01:00 -050012#include <fsl_qbman.h>
Kumar Gala38449a42009-09-10 03:02:13 -050013
Kumar Gala2b2b6962011-10-14 00:01:23 -050014struct srio_liodn_id_table {
15 u32 id[2];
16 unsigned long reg_offset[2];
17 u8 num_ids;
18 u8 portid;
19};
20#define SET_SRIO_LIODN_1(port, idA) \
21 { .id = { idA }, .num_ids = 1, .portid = port, \
22 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
Tom Rini6a5dccc2022-11-16 13:10:41 -050023 + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
Kumar Gala2b2b6962011-10-14 00:01:23 -050024 }
25
26#define SET_SRIO_LIODN_2(port, idA, idB) \
27 { .id = { idA, idB }, .num_ids = 2, .portid = port, \
28 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
Tom Rini6a5dccc2022-11-16 13:10:41 -050029 + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
Kumar Gala2b2b6962011-10-14 00:01:23 -050030 .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
Tom Rini6a5dccc2022-11-16 13:10:41 -050031 + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \
Kumar Gala2b2b6962011-10-14 00:01:23 -050032 }
33
Liu Gang1d5284b2013-06-25 18:12:12 +080034#define SET_SRIO_LIODN_BASE(port, id_a) \
35 { .id = { id_a }, .num_ids = 1, .portid = port, \
36 .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
37 + (port - 1) * 0x200 \
Tom Rini376b88a2022-10-28 20:27:13 -040038 + CFG_SYS_FSL_SRIO_ADDR, \
Liu Gang1d5284b2013-06-25 18:12:12 +080039 }
40
Kumar Gala38449a42009-09-10 03:02:13 -050041struct liodn_id_table {
42 const char * compat;
43 u32 id[2];
44 u8 num_ids;
45 phys_addr_t compat_offset;
46 unsigned long reg_offset;
47};
48
Igal Libermane14ec992015-08-18 14:47:05 +030049struct fman_liodn_id_table {
50 /* Freescale FMan Device Tree binding was updated for FMan.
51 * We need to support both new and old compatibles in order not to
52 * break backward compatibility.
53 */
54 const char *compat[2];
55 u32 id[2];
56 u8 num_ids;
57 phys_addr_t compat_offset;
58 unsigned long reg_offset;
59};
60
Kumar Gala38449a42009-09-10 03:02:13 -050061extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid);
62extern void set_liodns(void);
63extern void fdt_fixup_liodn(void *blob);
64
65#define SET_LIODN_BASE_1(idA) \
66 { .id = { idA }, .num_ids = 1, }
67
68#define SET_LIODN_BASE_2(idA, idB) \
69 { .id = { idA, idB }, .num_ids = 2 }
70
Igal Libermane14ec992015-08-18 14:47:05 +030071#define SET_FMAN_LIODN_ENTRY(name1, name2, idA, off, compatoff)\
72 { .compat[0] = name1, \
73 .compat[1] = name2, \
74 .id = { idA }, .num_ids = 1, \
Tom Rini6a5dccc2022-11-16 13:10:41 -050075 .reg_offset = off + CFG_SYS_CCSRBAR, \
76 .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
Igal Libermane14ec992015-08-18 14:47:05 +030077 }
78
Kumar Gala38449a42009-09-10 03:02:13 -050079#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
80 { .compat = name, \
81 .id = { idA }, .num_ids = 1, \
Tom Rini6a5dccc2022-11-16 13:10:41 -050082 .reg_offset = off + CFG_SYS_CCSRBAR, \
83 .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
Kumar Gala38449a42009-09-10 03:02:13 -050084 }
85
86#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
87 { .compat = name, \
88 .id = { idA, idB }, .num_ids = 2, \
Tom Rini6a5dccc2022-11-16 13:10:41 -050089 .reg_offset = off + CFG_SYS_CCSRBAR, \
90 .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
Kumar Gala38449a42009-09-10 03:02:13 -050091 }
92
93#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
94 SET_LIODN_ENTRY_1(compat, liodn, \
Tom Rinid5c3bf22022-10-28 20:27:12 -040095 offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \
Kumar Gala38449a42009-09-10 03:02:13 -050096 compatoff)
97
98#define SET_USB_LIODN(usbNum, compat, liodn) \
99 SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400100 CFG_SYS_MPC85xx_USB##usbNum##_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500101
102#define SET_SATA_LIODN(sataNum, liodn) \
103 SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400104 CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500105
Laurentiu TUDOR960f87f2011-03-15 16:37:36 +0200106#define SET_PCI_LIODN(compat, pciNum, liodn) \
107 SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400108 CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500109
Laurentiu Tudorb173eaf2012-10-05 09:48:51 +0000110#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
111 SET_LIODN_ENTRY_1(compat, liodn,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400112 offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
113 CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
Laurentiu Tudorb173eaf2012-10-05 09:48:51 +0000114
Kumar Gala38449a42009-09-10 03:02:13 -0500115/* reg nodes for DMA start @ 0x300 */
Tudor Laurentiu7210d9a2014-11-20 12:09:31 +0200116#define SET_DMA_LIODN(dmaNum, compat, liodn) \
117 SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400118 CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
Kumar Gala38449a42009-09-10 03:02:13 -0500119
120#define SET_SDHC_LIODN(sdhcNum, liodn) \
121 SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400122 CFG_SYS_MPC85xx_ESDHC_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500123
Zhao Qiangb818ba22014-03-21 16:21:45 +0800124#define SET_QE_LIODN(liodn) \
125 SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400126 CFG_SYS_MPC85xx_QE_OFFSET)
Zhao Qiangb818ba22014-03-21 16:21:45 +0800127
Sandeep Singh4fb16a12014-06-05 18:49:57 +0530128#define SET_TDM_LIODN(liodn) \
129 SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
Tom Rinid5c3bf22022-10-28 20:27:12 -0400130 CFG_SYS_MPC85xx_TDM_OFFSET)
Sandeep Singh4fb16a12014-06-05 18:49:57 +0530131
Kumar Gala38449a42009-09-10 03:02:13 -0500132#define SET_QMAN_LIODN(liodn) \
Ahmed Mansouraa270b42017-12-15 16:01:00 -0500133 SET_LIODN_ENTRY_1("fsl,qman", liodn, \
134 offsetof(struct ccsr_qman, liodnr) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400135 CFG_SYS_FSL_QMAN_OFFSET, \
136 CFG_SYS_FSL_QMAN_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500137
138#define SET_BMAN_LIODN(liodn) \
Ahmed Mansouraa270b42017-12-15 16:01:00 -0500139 SET_LIODN_ENTRY_1("fsl,bman", liodn, \
140 offsetof(struct ccsr_bman, liodnr) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400141 CFG_SYS_FSL_BMAN_OFFSET, \
142 CFG_SYS_FSL_BMAN_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500143
144#define SET_PME_LIODN(liodn) \
145 SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400146 CFG_SYS_FSL_CORENET_PME_OFFSET, \
147 CFG_SYS_FSL_CORENET_PME_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500148
Andy Fleming81177ad2012-10-08 07:44:18 +0000149#define SET_PMAN_LIODN(num, liodn) \
150 SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
151 offsetof(struct ccsr_pman, ppa1) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400152 CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
153 CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
Andy Fleming81177ad2012-10-08 07:44:18 +0000154
Kumar Gala38449a42009-09-10 03:02:13 -0500155/* -1 from portID due to how immap has the registers */
156#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
Tom Rini376b88a2022-10-28 20:27:13 -0400157 CFG_SYS_FSL_FM##fmNum##_OFFSET + \
Kumar Gala38449a42009-09-10 03:02:13 -0500158 offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
159
Igal Libermane14ec992015-08-18 14:47:05 +0300160#ifdef CONFIG_SYS_FMAN_V3
Kumar Gala38449a42009-09-10 03:02:13 -0500161/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
162#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
Igal Libermane14ec992015-08-18 14:47:05 +0300163 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
164 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
Tom Rini376b88a2022-10-28 20:27:13 -0400165 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500166
167/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
168#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
Igal Libermane14ec992015-08-18 14:47:05 +0300169 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
170 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
Tom Rini376b88a2022-10-28 20:27:13 -0400171 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
Kumar Gala38449a42009-09-10 03:02:13 -0500172
Shengzhou Liu0e24d3a2015-05-14 16:51:39 +0800173/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
174#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
Igal Libermane14ec992015-08-18 14:47:05 +0300175 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
176 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
Tom Rini376b88a2022-10-28 20:27:13 -0400177 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
Igal Libermane14ec992015-08-18 14:47:05 +0300178#else
179/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
180#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
181 SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
182 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
Tom Rini376b88a2022-10-28 20:27:13 -0400183 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
Shengzhou Liu0e24d3a2015-05-14 16:51:39 +0800184
Igal Libermane14ec992015-08-18 14:47:05 +0300185/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
186#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
187 SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
188 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
Tom Rini376b88a2022-10-28 20:27:13 -0400189 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
Igal Libermane14ec992015-08-18 14:47:05 +0300190#endif
Kim Phillipse49f1c32011-04-12 14:12:47 -0500191/*
192 * handle both old and new versioned SEC properties:
193 * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
194 */
Kumar Gala1c9cee92010-08-17 23:12:37 -0500195#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
196 SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
197 offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400198 CFG_SYS_FSL_SEC_OFFSET, \
199 CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
Kim Phillipse49f1c32011-04-12 14:12:47 -0500200 SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
201 offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400202 CFG_SYS_FSL_SEC_OFFSET, \
203 CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
Kumar Gala38449a42009-09-10 03:02:13 -0500204
205/* This is a bit evil since we treat rtic param as both a string & hex value */
206#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
207 SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
208 liodnA, \
209 offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400210 CFG_SYS_FSL_SEC_OFFSET, \
211 CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
Kim Phillipse49f1c32011-04-12 14:12:47 -0500212 SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
213 liodnA, \
214 offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400215 CFG_SYS_FSL_SEC_OFFSET, \
216 CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
Kumar Gala38449a42009-09-10 03:02:13 -0500217
218#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
219 SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
220 offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400221 CFG_SYS_FSL_SEC_OFFSET, 0)
Kumar Gala38449a42009-09-10 03:02:13 -0500222
Kumar Gala9d8e8132011-09-10 10:44:13 -0500223#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
224 SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
225 liodnA, \
226 offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400227 CFG_SYS_FSL_RAID_ENGINE_OFFSET, \
Kumar Gala9d8e8132011-09-10 10:44:13 -0500228 offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400229 CFG_SYS_FSL_RAID_ENGINE_OFFSET)
Kumar Gala9d8e8132011-09-10 10:44:13 -0500230
Kumar Gala4eb3c372011-10-14 13:28:52 -0500231#define SET_RMAN_LIODN(ibNum, liodn) \
232 SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
233 offsetof(struct ccsr_rman, mmitdr) + \
Tom Rini376b88a2022-10-28 20:27:13 -0400234 CFG_SYS_FSL_CORENET_RMAN_OFFSET, \
235 CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
Kumar Gala4eb3c372011-10-14 13:28:52 -0500236
Kumar Gala38449a42009-09-10 03:02:13 -0500237extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
Kumar Gala9d8e8132011-09-10 10:44:13 -0500238extern struct liodn_id_table raide_liodn_tbl[];
Igal Libermane14ec992015-08-18 14:47:05 +0300239extern struct fman_liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
Timur Tabiebede502012-10-05 09:48:52 +0000240#ifdef CONFIG_SYS_SRIO
Kumar Gala2b2b6962011-10-14 00:01:23 -0500241extern struct srio_liodn_id_table srio_liodn_tbl[];
Timur Tabiebede502012-10-05 09:48:52 +0000242extern int srio_liodn_tbl_sz;
243#endif
Kumar Gala4eb3c372011-10-14 13:28:52 -0500244extern struct liodn_id_table rman_liodn_tbl[];
Kumar Gala9d8e8132011-09-10 10:44:13 -0500245extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
Kumar Gala38449a42009-09-10 03:02:13 -0500246extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
Kumar Gala4eb3c372011-10-14 13:28:52 -0500247extern int rman_liodn_tbl_sz;
Kumar Gala38449a42009-09-10 03:02:13 -0500248
249#endif