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git01.mediatek.com / filogic / uboot / dececbb42cf7410984e26d9c4333e93b063f09d2 / . / arch / m68k / include / asm / immap_5275.h
blob: 9b8d71d30d44cd15f60bf1f2ddb6f2157c9d3952 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]2/*
3 * MCF5274/5 Internal Memory Map
4 *
5 * Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
6 * Based on work Copyright (c) 2003 Josef Baumgartner
7 * <josef.baumgartner@telex.de>
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]8 */
9
10#ifndef __IMMAP_5275__
11#define __IMMAP_5275__
12
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]13#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000)
14#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040)
15#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
16#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100)
17#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110)
18#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120)
19#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130)
20#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200)
21#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240)
22#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280)
23#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300)
24#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340)
25#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400)
26#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440)
27#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480)
28#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0)
29#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00)
30#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00)
31#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00)
32#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00001000)
33#define MMAP_FEC0FIFO (CFG_SYS_MBAR + 0x00001400)
34#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00001800)
35#define MMAP_FEC1FIFO (CFG_SYS_MBAR + 0x00001C00)
36#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000)
37#define MMAP_RCM (CFG_SYS_MBAR + 0x00110000)
38#define MMAP_CCM (CFG_SYS_MBAR + 0x00110004)
39#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000)
40#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000)
41#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000)
42#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000)
43#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000)
44#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000)
45#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000)
46#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000)
47#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000)
48#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000)
49#define MMAP_USB (CFG_SYS_MBAR + 0x001C0000)
50#define MMAP_PWM0 (CFG_SYS_MBAR + 0x001D0000)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]51
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000[diff] [blame]52#include <asm/coldfire/eport.h>
53#include <asm/coldfire/flexbus.h>
54#include <asm/coldfire/intctrl.h>
55#include <asm/coldfire/mdha.h>
56#include <asm/coldfire/pwm.h>
57#include <asm/coldfire/qspi.h>
58#include <asm/coldfire/rng.h>
59#include <asm/coldfire/skha.h>
60
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]61/* System configuration registers
62*/
63typedef struct sys_ctrl {
64 u32 ipsbar;
65 u32 res1;
66 u32 rambar;
67 u32 res2;
68 u8 crsr;
69 u8 cwcr;
70 u8 lpicr;
71 u8 cwsr;
72 u8 res3[8];
73 u32 mpark;
74 u8 mpr;
75 u8 res4[3];
76 u8 pacr0;
77 u8 pacr1;
78 u8 pacr2;
79 u8 pacr3;
80 u8 pacr4;
81 u8 res5;
82 u8 pacr5;
83 u8 pacr6;
84 u8 pacr7;
85 u8 res6;
86 u8 pacr8;
87 u8 res7;
88 u8 gpacr;
89 u8 res8[3];
90} sysctrl_t;
91/* SDRAM controller registers, offset: 0x040
92 */
93typedef struct sdram_ctrl {
94 u32 sdmr;
95 u32 sdcr;
96 u32 sdcfg1;
97 u32 sdcfg2;
98 u32 sdbar0;
99 u32 sdbmr0;
100 u32 sdbar1;
101 u32 sdbmr1;
102} sdramctrl_t;
103
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]104/* DMA module registers, offset 0x100
105 */
106typedef struct dma_ctrl {
107 u32 sar;
108 u32 dar;
109 u32 dsrbcr;
110 u32 dcr;
111} dma_t;
112
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]113/* GPIO port registers
114*/
115typedef struct gpio_ctrl {
116 /* Port Output Data Registers */
117 u8 podr_res1[4];
118 u8 podr_busctl;
119 u8 podr_addr;
120 u8 podr_res2[2];
121 u8 podr_cs;
122 u8 podr_res3;
123 u8 podr_fec0h;
124 u8 podr_fec0l;
125 u8 podr_feci2c;
126 u8 podr_qspi;
127 u8 podr_sdram;
128 u8 podr_timerh;
129 u8 podr_timerl;
130 u8 podr_uartl;
131 u8 podr_fec1h;
132 u8 podr_fec1l;
133 u8 podr_bs;
134 u8 podr_res4;
135 u8 podr_usbh;
136 u8 podr_usbl;
137 u8 podr_uarth;
138 u8 podr_res5[3];
139 /* Port Data Direction Registers */
140 u8 pddr_res1[4];
141 u8 pddr_busctl;
142 u8 pddr_addr;
143 u8 pddr_res2[2];
144 u8 pddr_cs;
145 u8 pddr_res3;
146 u8 pddr_fec0h;
147 u8 pddr_fec0l;
148 u8 pddr_feci2c;
149 u8 pddr_qspi;
150 u8 pddr_sdram;
151 u8 pddr_timerh;
152 u8 pddr_timerl;
153 u8 pddr_uartl;
154 u8 pddr_fec1h;
155 u8 pddr_fec1l;
156 u8 pddr_bs;
157 u8 pddr_res4;
158 u8 pddr_usbh;
159 u8 pddr_usbl;
160 u8 pddr_uarth;
161 u8 pddr_res5[3];
162 /* Port Pin Data/Set Registers */
163 u8 ppdsdr_res1[4];
164 u8 ppdsdr_busctl;
165 u8 ppdsdr_addr;
166 u8 ppdsdr_res2[2];
167 u8 ppdsdr_cs;
168 u8 ppdsdr_res3;
169 u8 ppdsdr_fec0h;
170 u8 ppdsdr_fec0l;
171 u8 ppdsdr_feci2c;
172 u8 ppdsdr_qspi;
173 u8 ppdsdr_sdram;
174 u8 ppdsdr_timerh;
175 u8 ppdsdr_timerl;
176 u8 ppdsdr_uartl;
177 u8 ppdsdr_fec1h;
178 u8 ppdsdr_fec1l;
179 u8 ppdsdr_bs;
180 u8 ppdsdr_res4;
181 u8 ppdsdr_usbh;
182 u8 ppdsdr_usbl;
183 u8 ppdsdr_uarth;
184 u8 ppdsdr_res5[3];
185 /* Port Clear Output Data Registers */
186 u8 pclrr_res1[4];
187 u8 pclrr_busctl;
188 u8 pclrr_addr;
189 u8 pclrr_res2[2];
190 u8 pclrr_cs;
191 u8 pclrr_res3;
192 u8 pclrr_fec0h;
193 u8 pclrr_fec0l;
194 u8 pclrr_feci2c;
195 u8 pclrr_qspi;
196 u8 pclrr_sdram;
197 u8 pclrr_timerh;
198 u8 pclrr_timerl;
199 u8 pclrr_uartl;
200 u8 pclrr_fec1h;
201 u8 pclrr_fec1l;
202 u8 pclrr_bs;
203 u8 pclrr_res4;
204 u8 pclrr_usbh;
205 u8 pclrr_usbl;
206 u8 pclrr_uarth;
207 u8 pclrr_res5[3];
208 /* Pin Assignment Registers */
209 u8 par_addr;
210 u8 par_cs;
211 u16 par_busctl;
212 u8 par_res1[2];
213 u16 par_usb;
214 u8 par_fec0hl;
215 u8 par_fec1hl;
216 u16 par_timer;
217 u16 par_uart;
218 u16 par_qspi;
219 u16 par_sdram;
220 u16 par_feci2c;
221 u8 par_bs;
222 u8 par_res2[3];
223} gpio_t;
224
225
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]226/* Watchdog registers
227 */
228typedef struct wdog_ctrl {
229 u16 wcr;
230 u16 wmr;
231 u16 wcntr;
232 u16 wsr;
233 u8 res4[114];
234} wdog_t;
235
236/* USB module registers
237*/
238typedef struct usb {
239 u16 res1;
240 u16 fnr;
241 u16 res2;
242 u16 fnmr;
243 u16 res3;
244 u16 rfmr;
245 u16 res4;
246 u16 rfmmr;
247 u8 res5[3];
248 u8 far;
249 u32 asr;
250 u32 drr1;
251 u32 drr2;
252 u16 res6;
253 u16 specr;
254 u16 res7;
255 u16 ep0sr;
256 u32 iep0cfg;
257 u32 oep0cfg;
258 u32 ep1cfg;
259 u32 ep2cfg;
260 u32 ep3cfg;
261 u32 ep4cfg;
262 u32 ep5cfg;
263 u32 ep6cfg;
264 u32 ep7cfg;
265 u32 ep0ctl;
266 u16 res8;
267 u16 ep1ctl;
268 u16 res9;
269 u16 ep2ctl;
270 u16 res10;
271 u16 ep3ctl;
272 u16 res11;
273 u16 ep4ctl;
274 u16 res12;
275 u16 ep5ctl;
276 u16 res13;
277 u16 ep6ctl;
278 u16 res14;
279 u16 ep7ctl;
280 u32 ep0isr;
281 u16 res15;
282 u16 ep1isr;
283 u16 res16;
284 u16 ep2isr;
285 u16 res17;
286 u16 ep3isr;
287 u16 res18;
288 u16 ep4isr;
289 u16 res19;
290 u16 ep5isr;
291 u16 res20;
292 u16 ep6isr;
293 u16 res21;
294 u16 ep7isr;
295 u32 ep0imr;
296 u16 res22;
297 u16 ep1imr;
298 u16 res23;
299 u16 ep2imr;
300 u16 res24;
301 u16 ep3imr;
302 u16 res25;
303 u16 ep4imr;
304 u16 res26;
305 u16 ep5imr;
306 u16 res27;
307 u16 ep6imr;
308 u16 res28;
309 u16 ep7imr;
310 u32 ep0dr;
311 u32 ep1dr;
312 u32 ep2dr;
313 u32 ep3dr;
314 u32 ep4dr;
315 u32 ep5dr;
316 u32 ep6dr;
317 u32 ep7dr;
318 u16 res29;
319 u16 ep0dpr;
320 u16 res30;
321 u16 ep1dpr;
322 u16 res31;
323 u16 ep2dpr;
324 u16 res32;
325 u16 ep3dpr;
326 u16 res33;
327 u16 ep4dpr;
328 u16 res34;
329 u16 ep5dpr;
330 u16 res35;
331 u16 ep6dpr;
332 u16 res36;
333 u16 ep7dpr;
334 u8 res37[788];
335 u8 cfgram[1024];
336} usb_t;
337
338/* PLL module registers
339 */
340typedef struct pll_ctrl {
341 u32 syncr;
342 u32 synsr;
343} pll_t;
344
345typedef struct rcm {
346 u8 rcr;
347 u8 rsr;
348} rcm_t;
349
350#endif /* __IMMAP_5275__ */