Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 2 | /* |
Timur Tabi | 2165c62 | 2009-09-04 16:28:35 -0500 | [diff] [blame] | 3 | * Copyright 2006,2009 Freescale Semiconductor, Inc. |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 4 | * |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 5 | * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 6 | * Changes for multibus/multiadapter I2C support. |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 7 | */ |
| 8 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame^] | 9 | #include <config.h> |
Jon Loeliger | 24df977 | 2006-10-19 12:02:24 -0500 | [diff] [blame] | 10 | #include <command.h> |
Jon Loeliger | 43d818f | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 11 | #include <i2c.h> /* Functional interface */ |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 12 | #include <log.h> |
Simon Glass | 45c7890 | 2019-11-14 12:57:26 -0700 | [diff] [blame] | 13 | #include <time.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 14 | #include <asm/global_data.h> |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 15 | #include <asm/io.h> |
Jon Loeliger | 43d818f | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 16 | #include <asm/fsl_i2c.h> /* HW definitions */ |
Mario Six | 2fe2ed6 | 2018-03-28 14:37:44 +0200 | [diff] [blame] | 17 | #include <clk.h> |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 18 | #include <dm.h> |
| 19 | #include <mapmem.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 20 | #include <linux/delay.h> |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 21 | |
Timur Tabi | 2165c62 | 2009-09-04 16:28:35 -0500 | [diff] [blame] | 22 | /* The maximum number of microseconds we will wait until another master has |
| 23 | * released the bus. If not defined in the board header file, then use a |
| 24 | * generic value. |
| 25 | */ |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 26 | #ifndef CFG_I2C_MBB_TIMEOUT |
| 27 | #define CFG_I2C_MBB_TIMEOUT 100000 |
Timur Tabi | 2165c62 | 2009-09-04 16:28:35 -0500 | [diff] [blame] | 28 | #endif |
| 29 | |
| 30 | /* The maximum number of microseconds we will wait for a read or write |
| 31 | * operation to complete. If not defined in the board header file, then use a |
| 32 | * generic value. |
| 33 | */ |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 34 | #ifndef CFG_I2C_TIMEOUT |
| 35 | #define CFG_I2C_TIMEOUT 100000 |
Timur Tabi | 2165c62 | 2009-09-04 16:28:35 -0500 | [diff] [blame] | 36 | #endif |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 37 | |
Joakim Tjernlund | c32c5f7 | 2006-11-28 16:17:27 -0600 | [diff] [blame] | 38 | #define I2C_READ_BIT 1 |
| 39 | #define I2C_WRITE_BIT 0 |
| 40 | |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 41 | DECLARE_GLOBAL_DATA_PTR; |
| 42 | |
Tom Rini | e9269a0 | 2021-12-12 22:12:30 -0500 | [diff] [blame] | 43 | #ifdef CONFIG_M68K |
Tom Rini | ef1b1f2 | 2023-01-10 11:19:30 -0500 | [diff] [blame] | 44 | #define CFG_FSL_I2C_BASE_ADDR CFG_SYS_MBAR |
| 45 | #else |
| 46 | #define CFG_FSL_I2C_BASE_ADDR CONFIG_SYS_IMMR |
Tom Rini | e9269a0 | 2021-12-12 22:12:30 -0500 | [diff] [blame] | 47 | #endif |
| 48 | |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 49 | #if !CONFIG_IS_ENABLED(DM_I2C) |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 50 | static const struct fsl_i2c_base *i2c_base[4] = { |
Tom Rini | ef1b1f2 | 2023-01-10 11:19:30 -0500 | [diff] [blame] | 51 | (struct fsl_i2c_base *)(CFG_FSL_I2C_BASE_ADDR + CONFIG_SYS_FSL_I2C_OFFSET), |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 52 | #ifdef CONFIG_SYS_FSL_I2C2_OFFSET |
Tom Rini | ef1b1f2 | 2023-01-10 11:19:30 -0500 | [diff] [blame] | 53 | (struct fsl_i2c_base *)(CFG_FSL_I2C_BASE_ADDR + CONFIG_SYS_FSL_I2C2_OFFSET), |
Shengzhou Liu | 37787f6 | 2014-07-07 12:17:48 +0800 | [diff] [blame] | 54 | #endif |
| 55 | #ifdef CONFIG_SYS_FSL_I2C3_OFFSET |
Tom Rini | ef1b1f2 | 2023-01-10 11:19:30 -0500 | [diff] [blame] | 56 | (struct fsl_i2c_base *)(CFG_FSL_I2C_BASE_ADDR + CONFIG_SYS_FSL_I2C3_OFFSET), |
Shengzhou Liu | 37787f6 | 2014-07-07 12:17:48 +0800 | [diff] [blame] | 57 | #endif |
| 58 | #ifdef CONFIG_SYS_FSL_I2C4_OFFSET |
Tom Rini | ef1b1f2 | 2023-01-10 11:19:30 -0500 | [diff] [blame] | 59 | (struct fsl_i2c_base *)(CFG_FSL_I2C_BASE_ADDR + CONFIG_SYS_FSL_I2C4_OFFSET) |
Timur Tabi | ab34754 | 2006-11-03 19:15:00 -0600 | [diff] [blame] | 60 | #endif |
| 61 | }; |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 62 | #endif |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 63 | |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 64 | /* I2C speed map for a DFSR value of 1 */ |
| 65 | |
Tom Rini | 56762c1 | 2017-02-09 15:40:16 -0500 | [diff] [blame] | 66 | #ifdef __M68K__ |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 67 | /* |
| 68 | * Map I2C frequency dividers to FDR and DFSR values |
| 69 | * |
| 70 | * This structure is used to define the elements of a table that maps I2C |
| 71 | * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be |
| 72 | * programmed into the Frequency Divider Ratio (FDR) and Digital Filter |
| 73 | * Sampling Rate (DFSR) registers. |
| 74 | * |
| 75 | * The actual table should be defined in the board file, and it must be called |
| 76 | * fsl_i2c_speed_map[]. |
| 77 | * |
| 78 | * The last entry of the table must have a value of {-1, X}, where X is same |
| 79 | * FDR/DFSR values as the second-to-last entry. This guarantees that any |
| 80 | * search through the array will always find a match. |
| 81 | * |
| 82 | * The values of the divider must be in increasing numerical order, i.e. |
| 83 | * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. |
| 84 | * |
| 85 | * For this table, the values are based on a value of 1 for the DFSR |
| 86 | * register. See the application note AN2919 "Determining the I2C Frequency |
| 87 | * Divider Ratio for SCL" |
TsiChung Liew | 00648a7 | 2008-08-19 00:56:46 +0600 | [diff] [blame] | 88 | * |
| 89 | * ColdFire I2C frequency dividers for FDR values are different from |
| 90 | * PowerPC. The protocol to use the I2C module is still the same. |
| 91 | * A different table is defined and are based on MCF5xxx user manual. |
| 92 | * |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 93 | */ |
| 94 | static const struct { |
| 95 | unsigned short divider; |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 96 | u8 fdr; |
| 97 | } fsl_i2c_speed_map[] = { |
TsiChung Liew | 00648a7 | 2008-08-19 00:56:46 +0600 | [diff] [blame] | 98 | {20, 32}, {22, 33}, {24, 34}, {26, 35}, |
| 99 | {28, 0}, {28, 36}, {30, 1}, {32, 37}, |
| 100 | {34, 2}, {36, 38}, {40, 3}, {40, 39}, |
| 101 | {44, 4}, {48, 5}, {48, 40}, {56, 6}, |
| 102 | {56, 41}, {64, 42}, {68, 7}, {72, 43}, |
| 103 | {80, 8}, {80, 44}, {88, 9}, {96, 41}, |
| 104 | {104, 10}, {112, 42}, {128, 11}, {128, 43}, |
| 105 | {144, 12}, {160, 13}, {160, 48}, {192, 14}, |
| 106 | {192, 49}, {224, 50}, {240, 15}, {256, 51}, |
| 107 | {288, 16}, {320, 17}, {320, 52}, {384, 18}, |
| 108 | {384, 53}, {448, 54}, {480, 19}, {512, 55}, |
| 109 | {576, 20}, {640, 21}, {640, 56}, {768, 22}, |
| 110 | {768, 57}, {960, 23}, {896, 58}, {1024, 59}, |
| 111 | {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, |
| 112 | {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, |
| 113 | {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, |
| 114 | {-1, 31} |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 115 | }; |
Tom Rini | 56762c1 | 2017-02-09 15:40:16 -0500 | [diff] [blame] | 116 | #endif |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 117 | |
| 118 | /** |
| 119 | * Set the I2C bus speed for a given I2C device |
| 120 | * |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 121 | * @param base: the I2C device registers |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 122 | * @i2c_clk: I2C bus clock frequency |
| 123 | * @speed: the desired speed of the bus |
| 124 | * |
| 125 | * The I2C device must be stopped before calling this function. |
| 126 | * |
| 127 | * The return value is the actual bus speed that is set. |
| 128 | */ |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 129 | static uint set_i2c_bus_speed(const struct fsl_i2c_base *base, |
| 130 | uint i2c_clk, uint speed) |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 131 | { |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 132 | ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX); |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 133 | |
| 134 | /* |
| 135 | * We want to choose an FDR/DFSR that generates an I2C bus speed that |
| 136 | * is equal to or lower than the requested speed. That means that we |
| 137 | * want the first divider that is equal to or greater than the |
| 138 | * calculated divider. |
| 139 | */ |
TsiChung Liew | 00648a7 | 2008-08-19 00:56:46 +0600 | [diff] [blame] | 140 | #ifdef __PPC__ |
Joakim Tjernlund | 5a6e061 | 2009-09-17 11:07:17 +0200 | [diff] [blame] | 141 | u8 dfsr, fdr = 0x31; /* Default if no FDR found */ |
| 142 | /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */ |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 143 | ushort a, b, ga, gb; |
| 144 | ulong c_div, est_div; |
Joakim Tjernlund | 5a6e061 | 2009-09-17 11:07:17 +0200 | [diff] [blame] | 145 | |
Joakim Tjernlund | e677e70 | 2009-09-17 11:07:16 +0200 | [diff] [blame] | 146 | #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR |
Joakim Tjernlund | 5a6e061 | 2009-09-17 11:07:17 +0200 | [diff] [blame] | 147 | dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; |
Joakim Tjernlund | e677e70 | 2009-09-17 11:07:16 +0200 | [diff] [blame] | 148 | #else |
Joakim Tjernlund | 5a6e061 | 2009-09-17 11:07:17 +0200 | [diff] [blame] | 149 | /* Condition 1: dfsr <= 50/T */ |
| 150 | dfsr = (5 * (i2c_clk / 1000)) / 100000; |
Joakim Tjernlund | e677e70 | 2009-09-17 11:07:16 +0200 | [diff] [blame] | 151 | #endif |
| 152 | #ifdef CONFIG_FSL_I2C_CUSTOM_FDR |
Joakim Tjernlund | 5a6e061 | 2009-09-17 11:07:17 +0200 | [diff] [blame] | 153 | fdr = CONFIG_FSL_I2C_CUSTOM_FDR; |
| 154 | speed = i2c_clk / divider; /* Fake something */ |
| 155 | #else |
| 156 | debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk); |
| 157 | if (!dfsr) |
| 158 | dfsr = 1; |
| 159 | |
| 160 | est_div = ~0; |
| 161 | for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) { |
| 162 | for (gb = 0; gb < 8; gb++) { |
| 163 | b = 16 << gb; |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 164 | c_div = b * (a + ((3 * dfsr) / b) * 2); |
| 165 | if (c_div > divider && c_div < est_div) { |
| 166 | ushort bin_gb, bin_ga; |
Joakim Tjernlund | 5a6e061 | 2009-09-17 11:07:17 +0200 | [diff] [blame] | 167 | |
| 168 | est_div = c_div; |
| 169 | bin_gb = gb << 2; |
| 170 | bin_ga = (ga & 0x3) | ((ga & 0x4) << 3); |
| 171 | fdr = bin_gb | bin_ga; |
| 172 | speed = i2c_clk / est_div; |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 173 | |
| 174 | debug("FDR: 0x%.2x, ", fdr); |
| 175 | debug("div: %ld, ", est_div); |
| 176 | debug("ga: 0x%x, gb: 0x%x, ", ga, gb); |
| 177 | debug("a: %d, b: %d, speed: %d\n", a, b, speed); |
| 178 | |
Joakim Tjernlund | 5a6e061 | 2009-09-17 11:07:17 +0200 | [diff] [blame] | 179 | /* Condition 2 not accounted for */ |
| 180 | debug("Tr <= %d ns\n", |
| 181 | (b - 3 * dfsr) * 1000000 / |
| 182 | (i2c_clk / 1000)); |
| 183 | } |
| 184 | } |
| 185 | if (a == 20) |
| 186 | a += 2; |
| 187 | if (a == 24) |
| 188 | a += 4; |
| 189 | } |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 190 | debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr); |
| 191 | debug("FDR: 0x%.2x, speed: %d\n", fdr, speed); |
Joakim Tjernlund | 5a6e061 | 2009-09-17 11:07:17 +0200 | [diff] [blame] | 192 | #endif |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 193 | writeb(dfsr, &base->dfsrr); /* set default filter */ |
| 194 | writeb(fdr, &base->fdr); /* set bus speed */ |
Joakim Tjernlund | e677e70 | 2009-09-17 11:07:16 +0200 | [diff] [blame] | 195 | #else |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 196 | uint i; |
Joakim Tjernlund | 5a6e061 | 2009-09-17 11:07:17 +0200 | [diff] [blame] | 197 | |
| 198 | for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) |
| 199 | if (fsl_i2c_speed_map[i].divider >= divider) { |
| 200 | u8 fdr; |
| 201 | |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 202 | fdr = fsl_i2c_speed_map[i].fdr; |
| 203 | speed = i2c_clk / fsl_i2c_speed_map[i].divider; |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 204 | writeb(fdr, &base->fdr); /* set bus speed */ |
Joakim Tjernlund | e677e70 | 2009-09-17 11:07:16 +0200 | [diff] [blame] | 205 | |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 206 | break; |
| 207 | } |
Joakim Tjernlund | 5a6e061 | 2009-09-17 11:07:17 +0200 | [diff] [blame] | 208 | #endif |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 209 | return speed; |
| 210 | } |
| 211 | |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 212 | #if !CONFIG_IS_ENABLED(DM_I2C) |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 213 | static uint get_i2c_clock(int bus) |
Jerry Huang | 5e01561 | 2011-10-26 15:29:38 +0000 | [diff] [blame] | 214 | { |
| 215 | if (bus) |
Simon Glass | c2baaec | 2012-12-13 20:48:49 +0000 | [diff] [blame] | 216 | return gd->arch.i2c2_clk; /* I2C2 clock */ |
Jerry Huang | 5e01561 | 2011-10-26 15:29:38 +0000 | [diff] [blame] | 217 | else |
Simon Glass | c2baaec | 2012-12-13 20:48:49 +0000 | [diff] [blame] | 218 | return gd->arch.i2c1_clk; /* I2C1 clock */ |
Jerry Huang | 5e01561 | 2011-10-26 15:29:38 +0000 | [diff] [blame] | 219 | } |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 220 | #endif |
Jerry Huang | 5e01561 | 2011-10-26 15:29:38 +0000 | [diff] [blame] | 221 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 222 | static int fsl_i2c_fixup(const struct fsl_i2c_base *base) |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 223 | { |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 224 | const unsigned long long timeout = usec2ticks(CFG_I2C_MBB_TIMEOUT); |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 225 | unsigned long long timeval = 0; |
| 226 | int ret = -1; |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 227 | uint flags = 0; |
Chunhe Lan | 9254640 | 2013-08-16 15:10:37 +0800 | [diff] [blame] | 228 | |
| 229 | #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 230 | uint svr = get_svr(); |
| 231 | |
Chunhe Lan | 9254640 | 2013-08-16 15:10:37 +0800 | [diff] [blame] | 232 | if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || |
| 233 | (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) |
| 234 | flags = I2C_CR_BIT6; |
| 235 | #endif |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 236 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 237 | writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr); |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 238 | |
| 239 | timeval = get_ticks(); |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 240 | while (!(readb(&base->sr) & I2C_SR_MBB)) { |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 241 | if ((get_ticks() - timeval) > timeout) |
| 242 | goto err; |
| 243 | } |
| 244 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 245 | if (readb(&base->sr) & I2C_SR_MAL) { |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 246 | /* SDA is stuck low */ |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 247 | writeb(0, &base->cr); |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 248 | udelay(100); |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 249 | writeb(I2C_CR_MSTA | flags, &base->cr); |
| 250 | writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr); |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 251 | } |
| 252 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 253 | readb(&base->dr); |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 254 | |
| 255 | timeval = get_ticks(); |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 256 | while (!(readb(&base->sr) & I2C_SR_MIF)) { |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 257 | if ((get_ticks() - timeval) > timeout) |
| 258 | goto err; |
| 259 | } |
| 260 | ret = 0; |
| 261 | |
| 262 | err: |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 263 | writeb(I2C_CR_MEN | flags, &base->cr); |
| 264 | writeb(0, &base->sr); |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 265 | udelay(100); |
| 266 | |
| 267 | return ret; |
| 268 | } |
| 269 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 270 | static void __i2c_init(const struct fsl_i2c_base *base, int speed, int |
| 271 | slaveadd, int i2c_clk, int busnum) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 272 | { |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 273 | const unsigned long long timeout = usec2ticks(CFG_I2C_MBB_TIMEOUT); |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 274 | unsigned long long timeval; |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 275 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 276 | writeb(0, &base->cr); /* stop I2C controller */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 277 | udelay(5); /* let it shutdown in peace */ |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 278 | set_i2c_bus_speed(base, i2c_clk, speed); |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 279 | writeb(slaveadd << 1, &base->adr);/* write slave address */ |
| 280 | writeb(0x0, &base->sr); /* clear status register */ |
Angelo Dureghello | 6f88ce2 | 2023-04-05 00:59:26 +0200 | [diff] [blame] | 281 | /* start I2C controller */ |
| 282 | writeb(I2C_CR_MEN | I2C_CR_MIEN, &base->cr); |
Richard Retanubun | df0149c | 2010-04-12 15:08:17 -0400 | [diff] [blame] | 283 | |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 284 | timeval = get_ticks(); |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 285 | while (readb(&base->sr) & I2C_SR_MBB) { |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 286 | if ((get_ticks() - timeval) < timeout) |
| 287 | continue; |
| 288 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 289 | if (fsl_i2c_fixup(base)) |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 290 | debug("i2c_init: BUS#%d failed to init\n", |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 291 | busnum); |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 292 | |
| 293 | break; |
| 294 | } |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 295 | } |
| 296 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 297 | static int i2c_wait4bus(const struct fsl_i2c_base *base) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 298 | { |
Stefan Roese | 3762825 | 2008-08-06 14:05:38 +0200 | [diff] [blame] | 299 | unsigned long long timeval = get_ticks(); |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 300 | const unsigned long long timeout = usec2ticks(CFG_I2C_MBB_TIMEOUT); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 301 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 302 | while (readb(&base->sr) & I2C_SR_MBB) { |
Timur Tabi | 2165c62 | 2009-09-04 16:28:35 -0500 | [diff] [blame] | 303 | if ((get_ticks() - timeval) > timeout) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 304 | return -1; |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
Mario Six | 484cdb8 | 2018-01-15 11:08:08 +0100 | [diff] [blame] | 310 | static int i2c_wait(const struct fsl_i2c_base *base, int write) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 311 | { |
| 312 | u32 csr; |
Stefan Roese | 3762825 | 2008-08-06 14:05:38 +0200 | [diff] [blame] | 313 | unsigned long long timeval = get_ticks(); |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 314 | const unsigned long long timeout = usec2ticks(CFG_I2C_TIMEOUT); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 315 | |
| 316 | do { |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 317 | csr = readb(&base->sr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 318 | if (!(csr & I2C_SR_MIF)) |
| 319 | continue; |
Joakim Tjernlund | c324b78 | 2009-09-17 11:07:15 +0200 | [diff] [blame] | 320 | /* Read again to allow register to stabilise */ |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 321 | csr = readb(&base->sr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 322 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 323 | writeb(0x0, &base->sr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 324 | |
| 325 | if (csr & I2C_SR_MAL) { |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 326 | debug("%s: MAL\n", __func__); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 327 | return -1; |
| 328 | } |
| 329 | |
| 330 | if (!(csr & I2C_SR_MCF)) { |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 331 | debug("%s: unfinished\n", __func__); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 332 | return -1; |
| 333 | } |
| 334 | |
Joakim Tjernlund | c32c5f7 | 2006-11-28 16:17:27 -0600 | [diff] [blame] | 335 | if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 336 | debug("%s: No RXACK\n", __func__); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 337 | return -1; |
| 338 | } |
| 339 | |
| 340 | return 0; |
Timur Tabi | 2165c62 | 2009-09-04 16:28:35 -0500 | [diff] [blame] | 341 | } while ((get_ticks() - timeval) < timeout); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 342 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 343 | debug("%s: timed out\n", __func__); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 344 | return -1; |
| 345 | } |
| 346 | |
Mario Six | 484cdb8 | 2018-01-15 11:08:08 +0100 | [diff] [blame] | 347 | static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, |
| 348 | u8 dir, int rsta) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 349 | { |
Angelo Dureghello | 6f88ce2 | 2023-04-05 00:59:26 +0200 | [diff] [blame] | 350 | writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA | I2C_CR_MTX |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 351 | | (rsta ? I2C_CR_RSTA : 0), |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 352 | &base->cr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 353 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 354 | writeb((dev << 1) | dir, &base->dr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 355 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 356 | if (i2c_wait(base, I2C_WRITE_BIT) < 0) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 357 | return 0; |
| 358 | |
| 359 | return 1; |
| 360 | } |
| 361 | |
Mario Six | 484cdb8 | 2018-01-15 11:08:08 +0100 | [diff] [blame] | 362 | static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, |
| 363 | int length) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 364 | { |
| 365 | int i; |
| 366 | |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 367 | for (i = 0; i < length; i++) { |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 368 | writeb(data[i], &base->dr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 369 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 370 | if (i2c_wait(base, I2C_WRITE_BIT) < 0) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 371 | break; |
| 372 | } |
| 373 | |
| 374 | return i; |
| 375 | } |
| 376 | |
Mario Six | 484cdb8 | 2018-01-15 11:08:08 +0100 | [diff] [blame] | 377 | static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, |
| 378 | int length) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 379 | { |
| 380 | int i; |
| 381 | |
Angelo Dureghello | 6f88ce2 | 2023-04-05 00:59:26 +0200 | [diff] [blame] | 382 | writeb(I2C_CR_MEN | I2C_CR_MIEN | |
| 383 | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 384 | &base->cr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 385 | |
| 386 | /* dummy read */ |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 387 | readb(&base->dr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 388 | |
| 389 | for (i = 0; i < length; i++) { |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 390 | if (i2c_wait(base, I2C_READ_BIT) < 0) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 391 | break; |
| 392 | |
| 393 | /* Generate ack on last next to last byte */ |
| 394 | if (i == length - 2) |
Angelo Dureghello | 6f88ce2 | 2023-04-05 00:59:26 +0200 | [diff] [blame] | 395 | writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA | |
| 396 | I2C_CR_TXAK, &base->cr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 397 | |
Joakim Tjernlund | 6384da2 | 2009-09-22 13:40:44 +0200 | [diff] [blame] | 398 | /* Do not generate stop on last byte */ |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 399 | if (i == length - 1) |
Angelo Dureghello | 6f88ce2 | 2023-04-05 00:59:26 +0200 | [diff] [blame] | 400 | writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA | |
| 401 | I2C_CR_MTX, &base->cr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 402 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 403 | data[i] = readb(&base->dr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | return i; |
| 407 | } |
| 408 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 409 | static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, |
| 410 | int olen, u8 *data, int dlen) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 411 | { |
mario.six@gdsys.cc | a447265 | 2016-04-25 08:31:02 +0200 | [diff] [blame] | 412 | int ret = -1; /* signal error */ |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 413 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 414 | if (i2c_wait4bus(base) < 0) |
Reinhard Pfau | 2d878de | 2013-06-26 15:55:14 +0200 | [diff] [blame] | 415 | return -1; |
| 416 | |
mario.six@gdsys.cc | 2eae9d0 | 2016-04-25 08:31:03 +0200 | [diff] [blame] | 417 | /* Some drivers use offset lengths in excess of 4 bytes. These drivers |
| 418 | * adhere to the following convention: |
| 419 | * - the offset length is passed as negative (that is, the absolute |
| 420 | * value of olen is the actual offset length) |
| 421 | * - the offset itself is passed in data, which is overwritten by the |
| 422 | * subsequent read operation |
Shaveta Leekha | fdd7efe | 2014-04-24 14:51:23 +0530 | [diff] [blame] | 423 | */ |
mario.six@gdsys.cc | a447265 | 2016-04-25 08:31:02 +0200 | [diff] [blame] | 424 | if (olen < 0) { |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 425 | if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0) |
| 426 | ret = __i2c_write_data(base, data, -olen); |
Shaveta Leekha | fdd7efe | 2014-04-24 14:51:23 +0530 | [diff] [blame] | 427 | |
mario.six@gdsys.cc | 8230fc4 | 2016-04-25 08:31:04 +0200 | [diff] [blame] | 428 | if (ret != -olen) |
Shaveta Leekha | fdd7efe | 2014-04-24 14:51:23 +0530 | [diff] [blame] | 429 | return -1; |
| 430 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 431 | if (dlen && i2c_write_addr(base, chip_addr, |
mario.six@gdsys.cc | a447265 | 2016-04-25 08:31:02 +0200 | [diff] [blame] | 432 | I2C_READ_BIT, 1) != 0) |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 433 | ret = __i2c_read_data(base, data, dlen); |
Shaveta Leekha | fdd7efe | 2014-04-24 14:51:23 +0530 | [diff] [blame] | 434 | } else { |
mario.six@gdsys.cc | a447265 | 2016-04-25 08:31:02 +0200 | [diff] [blame] | 435 | if ((!dlen || olen > 0) && |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 436 | i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 && |
| 437 | __i2c_write_data(base, offset, olen) == olen) |
mario.six@gdsys.cc | a447265 | 2016-04-25 08:31:02 +0200 | [diff] [blame] | 438 | ret = 0; /* No error so far */ |
Joakim Tjernlund | b648fe7 | 2007-01-31 11:04:19 +0100 | [diff] [blame] | 439 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 440 | if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT, |
mario.six@gdsys.cc | a447265 | 2016-04-25 08:31:02 +0200 | [diff] [blame] | 441 | olen ? 1 : 0) != 0) |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 442 | ret = __i2c_read_data(base, data, dlen); |
Shaveta Leekha | fdd7efe | 2014-04-24 14:51:23 +0530 | [diff] [blame] | 443 | } |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 444 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 445 | writeb(I2C_CR_MEN, &base->cr); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 446 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 447 | if (i2c_wait4bus(base)) /* Wait until STOP */ |
Joakim Tjernlund | 6384da2 | 2009-09-22 13:40:44 +0200 | [diff] [blame] | 448 | debug("i2c_read: wait4bus timed out\n"); |
| 449 | |
mario.six@gdsys.cc | a447265 | 2016-04-25 08:31:02 +0200 | [diff] [blame] | 450 | if (ret == dlen) |
| 451 | return 0; |
Jon Loeliger | 24df977 | 2006-10-19 12:02:24 -0500 | [diff] [blame] | 452 | |
| 453 | return -1; |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 454 | } |
| 455 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 456 | static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, |
| 457 | u8 *offset, int olen, u8 *data, int dlen) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 458 | { |
mario.six@gdsys.cc | a447265 | 2016-04-25 08:31:02 +0200 | [diff] [blame] | 459 | int ret = -1; /* signal error */ |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 460 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 461 | if (i2c_wait4bus(base) < 0) |
Chunhe Lan | 2e13d57 | 2013-08-16 15:10:36 +0800 | [diff] [blame] | 462 | return -1; |
| 463 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 464 | if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 && |
| 465 | __i2c_write_data(base, offset, olen) == olen) { |
| 466 | ret = __i2c_write_data(base, data, dlen); |
Jon Loeliger | 24df977 | 2006-10-19 12:02:24 -0500 | [diff] [blame] | 467 | } |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 468 | |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 469 | writeb(I2C_CR_MEN, &base->cr); |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 470 | if (i2c_wait4bus(base)) /* Wait until STOP */ |
Joakim Tjernlund | c324b78 | 2009-09-17 11:07:15 +0200 | [diff] [blame] | 471 | debug("i2c_write: wait4bus timed out\n"); |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 472 | |
mario.six@gdsys.cc | a447265 | 2016-04-25 08:31:02 +0200 | [diff] [blame] | 473 | if (ret == dlen) |
| 474 | return 0; |
Jon Loeliger | 24df977 | 2006-10-19 12:02:24 -0500 | [diff] [blame] | 475 | |
| 476 | return -1; |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 477 | } |
| 478 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 479 | static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 480 | { |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 481 | /* For unknown reason the controller will ACK when |
Joakim Tjernlund | b648fe7 | 2007-01-31 11:04:19 +0100 | [diff] [blame] | 482 | * probing for a slave with the same address, so skip |
| 483 | * it. |
Jon Loeliger | e4773be | 2006-10-19 11:02:16 -0500 | [diff] [blame] | 484 | */ |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 485 | if (chip == (readb(&base->adr) >> 1)) |
Timur Tabi | ab34754 | 2006-11-03 19:15:00 -0600 | [diff] [blame] | 486 | return -1; |
Timur Tabi | ab34754 | 2006-11-03 19:15:00 -0600 | [diff] [blame] | 487 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 488 | return __i2c_read(base, chip, 0, 0, NULL, 0); |
Timur Tabi | ab34754 | 2006-11-03 19:15:00 -0600 | [diff] [blame] | 489 | } |
| 490 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 491 | static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base, |
| 492 | uint speed, int i2c_clk) |
Timur Tabi | ab34754 | 2006-11-03 19:15:00 -0600 | [diff] [blame] | 493 | { |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 494 | writeb(0, &base->cr); /* stop controller */ |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 495 | set_i2c_bus_speed(base, i2c_clk, speed); |
mario.six@gdsys.cc | 7d43b4e | 2016-04-25 08:31:01 +0200 | [diff] [blame] | 496 | writeb(I2C_CR_MEN, &base->cr); /* start controller */ |
Timur Tabi | b301fda | 2008-03-14 17:45:29 -0500 | [diff] [blame] | 497 | |
| 498 | return 0; |
Timur Tabi | ab34754 | 2006-11-03 19:15:00 -0600 | [diff] [blame] | 499 | } |
| 500 | |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 501 | #if !CONFIG_IS_ENABLED(DM_I2C) |
mario.six@gdsys.cc | 2d96aa7 | 2016-04-25 08:31:07 +0200 | [diff] [blame] | 502 | static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) |
| 503 | { |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 504 | __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd, |
| 505 | get_i2c_clock(adap->hwadapnr), adap->hwadapnr); |
mario.six@gdsys.cc | 2d96aa7 | 2016-04-25 08:31:07 +0200 | [diff] [blame] | 506 | } |
| 507 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 508 | static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip) |
mario.six@gdsys.cc | 2d96aa7 | 2016-04-25 08:31:07 +0200 | [diff] [blame] | 509 | { |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 510 | return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip); |
mario.six@gdsys.cc | 2d96aa7 | 2016-04-25 08:31:07 +0200 | [diff] [blame] | 511 | } |
| 512 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 513 | static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, |
| 514 | int olen, u8 *data, int dlen) |
mario.six@gdsys.cc | 2d96aa7 | 2016-04-25 08:31:07 +0200 | [diff] [blame] | 515 | { |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 516 | u8 *o = (u8 *)&offset; |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 517 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 518 | return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], |
| 519 | olen, data, dlen); |
mario.six@gdsys.cc | 2d96aa7 | 2016-04-25 08:31:07 +0200 | [diff] [blame] | 520 | } |
| 521 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 522 | static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, |
| 523 | int olen, u8 *data, int dlen) |
mario.six@gdsys.cc | 2d96aa7 | 2016-04-25 08:31:07 +0200 | [diff] [blame] | 524 | { |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 525 | u8 *o = (u8 *)&offset; |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 526 | |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 527 | return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], |
| 528 | olen, data, dlen); |
mario.six@gdsys.cc | 2d96aa7 | 2016-04-25 08:31:07 +0200 | [diff] [blame] | 529 | } |
| 530 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 531 | static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) |
mario.six@gdsys.cc | 2d96aa7 | 2016-04-25 08:31:07 +0200 | [diff] [blame] | 532 | { |
mario.six@gdsys.cc | 416b2dc | 2016-04-25 08:31:08 +0200 | [diff] [blame] | 533 | return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed, |
| 534 | get_i2c_clock(adap->hwadapnr)); |
mario.six@gdsys.cc | 2d96aa7 | 2016-04-25 08:31:07 +0200 | [diff] [blame] | 535 | } |
| 536 | |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 537 | /* |
| 538 | * Register fsl i2c adapters |
| 539 | */ |
mario.six@gdsys.cc | 4a79069 | 2016-04-25 08:31:05 +0200 | [diff] [blame] | 540 | U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 541 | fsl_i2c_write, fsl_i2c_set_bus_speed, |
Tom Rini | be94c76 | 2021-08-18 23:12:35 -0400 | [diff] [blame] | 542 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 543 | 0) |
| 544 | #ifdef CONFIG_SYS_FSL_I2C2_OFFSET |
mario.six@gdsys.cc | 4a79069 | 2016-04-25 08:31:05 +0200 | [diff] [blame] | 545 | U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 546 | fsl_i2c_write, fsl_i2c_set_bus_speed, |
Tom Rini | be94c76 | 2021-08-18 23:12:35 -0400 | [diff] [blame] | 547 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 548 | 1) |
Heiko Schocher | 2c9f3a4 | 2009-02-24 11:30:37 +0100 | [diff] [blame] | 549 | #endif |
Shengzhou Liu | 37787f6 | 2014-07-07 12:17:48 +0800 | [diff] [blame] | 550 | #ifdef CONFIG_SYS_FSL_I2C3_OFFSET |
mario.six@gdsys.cc | 4a79069 | 2016-04-25 08:31:05 +0200 | [diff] [blame] | 551 | U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, |
Shengzhou Liu | 37787f6 | 2014-07-07 12:17:48 +0800 | [diff] [blame] | 552 | fsl_i2c_write, fsl_i2c_set_bus_speed, |
Tom Rini | be94c76 | 2021-08-18 23:12:35 -0400 | [diff] [blame] | 553 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, |
Shengzhou Liu | 37787f6 | 2014-07-07 12:17:48 +0800 | [diff] [blame] | 554 | 2) |
| 555 | #endif |
| 556 | #ifdef CONFIG_SYS_FSL_I2C4_OFFSET |
mario.six@gdsys.cc | 4a79069 | 2016-04-25 08:31:05 +0200 | [diff] [blame] | 557 | U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, |
Shengzhou Liu | 37787f6 | 2014-07-07 12:17:48 +0800 | [diff] [blame] | 558 | fsl_i2c_write, fsl_i2c_set_bus_speed, |
Tom Rini | be94c76 | 2021-08-18 23:12:35 -0400 | [diff] [blame] | 559 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, |
Shengzhou Liu | 37787f6 | 2014-07-07 12:17:48 +0800 | [diff] [blame] | 560 | 3) |
| 561 | #endif |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 562 | #else /* CONFIG_DM_I2C */ |
| 563 | static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr, |
| 564 | u32 chip_flags) |
| 565 | { |
| 566 | struct fsl_i2c_dev *dev = dev_get_priv(bus); |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 567 | |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 568 | return __i2c_probe_chip(dev->base, chip_addr); |
| 569 | } |
| 570 | |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 571 | static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed) |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 572 | { |
| 573 | struct fsl_i2c_dev *dev = dev_get_priv(bus); |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 574 | |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 575 | return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk); |
| 576 | } |
| 577 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 578 | static int fsl_i2c_of_to_plat(struct udevice *bus) |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 579 | { |
| 580 | struct fsl_i2c_dev *dev = dev_get_priv(bus); |
Mario Six | 2fe2ed6 | 2018-03-28 14:37:44 +0200 | [diff] [blame] | 581 | struct clk clock; |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 582 | |
Mario Six | 486b2d5 | 2018-03-28 14:37:43 +0200 | [diff] [blame] | 583 | dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base)); |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 584 | |
| 585 | if (!dev->base) |
| 586 | return -ENOMEM; |
| 587 | |
Mario Six | 84b68b8 | 2018-01-15 11:08:09 +0100 | [diff] [blame] | 588 | dev->index = dev_read_u32_default(bus, "cell-index", -1); |
| 589 | dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr", |
| 590 | 0x7f); |
Simon Glass | f0c99c5 | 2020-01-23 11:48:22 -0700 | [diff] [blame] | 591 | dev->speed = dev_read_u32_default(bus, "clock-frequency", |
| 592 | I2C_SPEED_FAST_RATE); |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 593 | |
Mario Six | 2fe2ed6 | 2018-03-28 14:37:44 +0200 | [diff] [blame] | 594 | if (!clk_get_by_index(bus, 0, &clock)) |
| 595 | dev->i2c_clk = clk_get_rate(&clock); |
| 596 | else |
| 597 | dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : |
| 598 | gd->arch.i2c1_clk; |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 599 | |
| 600 | return 0; |
| 601 | } |
| 602 | |
| 603 | static int fsl_i2c_probe(struct udevice *bus) |
| 604 | { |
| 605 | struct fsl_i2c_dev *dev = dev_get_priv(bus); |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 606 | |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 607 | __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk, |
| 608 | dev->index); |
| 609 | return 0; |
| 610 | } |
| 611 | |
| 612 | static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) |
| 613 | { |
| 614 | struct fsl_i2c_dev *dev = dev_get_priv(bus); |
| 615 | struct i2c_msg *dmsg, *omsg, dummy; |
| 616 | |
| 617 | memset(&dummy, 0, sizeof(struct i2c_msg)); |
| 618 | |
| 619 | /* We expect either two messages (one with an offset and one with the |
Mario Six | a5f35c4 | 2018-01-15 11:08:07 +0100 | [diff] [blame] | 620 | * actual data) or one message (just data) |
| 621 | */ |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 622 | if (nmsgs > 2 || nmsgs == 0) { |
| 623 | debug("%s: Only one or two messages are supported.", __func__); |
| 624 | return -1; |
| 625 | } |
| 626 | |
| 627 | omsg = nmsgs == 1 ? &dummy : msg; |
| 628 | dmsg = nmsgs == 1 ? msg : msg + 1; |
| 629 | |
| 630 | if (dmsg->flags & I2C_M_RD) |
| 631 | return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len, |
| 632 | dmsg->buf, dmsg->len); |
| 633 | else |
| 634 | return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len, |
| 635 | dmsg->buf, dmsg->len); |
| 636 | } |
| 637 | |
| 638 | static const struct dm_i2c_ops fsl_i2c_ops = { |
| 639 | .xfer = fsl_i2c_xfer, |
| 640 | .probe_chip = fsl_i2c_probe_chip, |
| 641 | .set_bus_speed = fsl_i2c_set_bus_speed, |
| 642 | }; |
| 643 | |
| 644 | static const struct udevice_id fsl_i2c_ids[] = { |
| 645 | { .compatible = "fsl-i2c", }, |
| 646 | { /* sentinel */ } |
| 647 | }; |
| 648 | |
| 649 | U_BOOT_DRIVER(i2c_fsl) = { |
| 650 | .name = "i2c_fsl", |
| 651 | .id = UCLASS_I2C, |
| 652 | .of_match = fsl_i2c_ids, |
| 653 | .probe = fsl_i2c_probe, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 654 | .of_to_plat = fsl_i2c_of_to_plat, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 655 | .priv_auto = sizeof(struct fsl_i2c_dev), |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 656 | .ops = &fsl_i2c_ops, |
| 657 | }; |
| 658 | |
| 659 | #endif /* CONFIG_DM_I2C */ |