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git01.mediatek.com / filogic / uboot / dec7ea0d173ac494196b5635e125e6973b55ea1f / . / drivers / clk / adi / clk-adi-sc598.c
blob: d4a16ac9603bd42a9a8b628a37c4c7e70d18310f [file] [log] [blame]
Tom Rinidec7ea02024-05-20 13:35:03 -0600[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * (C) Copyright 2022 - Analog Devices, Inc.
4 *
5 * Written and/or maintained by Timesys Corporation
6 *
7 * Author: Greg Malysa <greg.malysa@timesys.com>
8 *
9 * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
10 */
11
12#include <clk.h>
13#include <clk-uclass.h>
14#include <dm.h>
15#include <dt-bindings/clock/adi-sc5xx-clock.h>
16#include <linux/compiler_types.h>
17#include <linux/clk-provider.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/printk.h>
21#include <linux/types.h>
22
23#include "clk.h"
24
25static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"};
26static const char * const cgu0_s1sels[] = {"cgu0_s1seldiv", "cgu0_s1selexdiv"};
27static const char * const cgu1_s0sels[] = {"cgu1_s0seldiv", "cgu1_s0selexdiv"};
28static const char * const cgu1_s1sels[] = {"cgu1_s1seldiv", "cgu1_s1selexdiv"};
29static const char * const sharc0_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"};
30static const char * const sharc1_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"};
31static const char * const arm_sels[] = {"dummy", "dummy", "cclk2_0", "cclk2_1"};
32static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"};
33static const char * const can_sels[] = {"dummy", "oclk_1", "dummy", "dummy"};
34static const char * const spdif_sels[] = {"sclk1_0", "dummy", "dummy", "dummy"};
35static const char * const spi_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"};
36static const char * const gige_sels[] = {"sclk0_0", "sclk0_1", "dummy", "dummy"};
37static const char * const lp_sels[] = {"oclk_0", "sclk0_0", "cclk0_1", "dummy"};
38static const char * const lp_ddr_sels[] = {"oclk_0", "dclk_0", "sysclk_1", "dummy"};
39static const char * const ospi_refclk_sels[] = {"sysclk_0", "sclk0_0", "sclk1_1",
40 "dummy"};
41static const char * const trace_sels[] = {"sclk0_0", "dummy", "dummy", "dummy"};
42static const char * const emmc_sels[] = {"oclk_0", "sclk0_1", "dclk_0_half",
43 "dclk_1_half"};
44static const char * const emmc_timer_sels[] = {"dummy", "sclk1_1_half", "dummy",
45 "dummy"};
46static const char * const ddr_sels[] = {"cdu_ddr", "3pll_ddiv"};
47
48static int sc598_clock_probe(struct udevice *dev)
49{
50 void __iomem *cgu0;
51 void __iomem *cgu1;
52 void __iomem *cdu;
53 void __iomem *pll3;
54 int ret;
55 struct resource res;
56
57 struct clk *clks[ADSP_SC598_CLK_END];
58 struct clk dummy, clkin0, clkin1;
59
60 ret = dev_read_resource_byname(dev, "cgu0", &res);
61 if (ret)
62 return ret;
63 cgu0 = devm_ioremap(dev, res.start, resource_size(&res));
64
65 ret = dev_read_resource_byname(dev, "cgu1", &res);
66 if (ret)
67 return ret;
68 cgu1 = devm_ioremap(dev, res.start, resource_size(&res));
69
70 ret = dev_read_resource_byname(dev, "cdu", &res);
71 if (ret)
72 return ret;
73 cdu = devm_ioremap(dev, res.start, resource_size(&res));
74
75 ret = dev_read_resource_byname(dev, "pll3", &res);
76 if (ret)
77 return ret;
78 pll3 = devm_ioremap(dev, res.start, resource_size(&res));
79
80 // We only access this one register for pll3
81 pll3 = pll3 + PLL3_OFFSET;
82
83 // Input clock configuration
84 clk_get_by_name(dev, "dummy", &dummy);
85 clk_get_by_name(dev, "sys_clkin0", &clkin0);
86 clk_get_by_name(dev, "sys_clkin1", &clkin1);
87
88 clks[ADSP_SC598_CLK_DUMMY] = &dummy;
89 clks[ADSP_SC598_CLK_SYS_CLKIN0] = &clkin0;
90 clks[ADSP_SC598_CLK_SYS_CLKIN1] = &clkin1;
91
92 clks[ADSP_SC598_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels,
93 2, CLK_SET_RATE_PARENT,
94 cdu + CDU_CLKINSEL, 0, 1, 0);
95
96 // 3rd pll reuses cgu1 clk in selection, feeds directly into 3pll df
97 // changing the cgu1 in sel mux will affect 3pll so reuse the same clocks
98
99 // CGU configuration and internal clocks
100 clks[ADSP_SC598_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df",
101 "sys_clkin0",
102 CLK_SET_RATE_PARENT,
103 cgu0 + CGU_CTL, 0, 1, 0);
104 clks[ADSP_SC598_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df",
105 "cgu1_in_sel",
106 CLK_SET_RATE_PARENT,
107 cgu1 + CGU_CTL, 0, 1, 0);
108 clks[ADSP_SC598_CLK_3PLL_PLL_IN] = clk_register_divider(NULL, "3pll_df",
109 "cgu1_in_sel",
110 CLK_SET_RATE_PARENT,
111 pll3, 3, 1, 0);
112
113 // VCO output inside PLL
114 clks[ADSP_SC598_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df",
115 cgu0 + CGU_CTL, CGU_MSEL_SHIFT,
116 CGU_MSEL_WIDTH, 0, true);
117 clks[ADSP_SC598_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df",
118 cgu1 + CGU_CTL, CGU_MSEL_SHIFT,
119 CGU_MSEL_WIDTH, 0, true);
120 clks[ADSP_SC598_CLK_3PLL_VCO_OUT] = sc5xx_cgu_pll("3pll_vco", "3pll_df",
121 pll3, PLL3_MSEL_SHIFT,
122 PLL3_MSEL_WIDTH, 1, true);
123
124 // Final PLL output
125 clks[ADSP_SC598_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk",
126 "cgu0_vco",
127 CLK_SET_RATE_PARENT,
128 1, 2);
129 clks[ADSP_SC598_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk",
130 "cgu1_vco",
131 CLK_SET_RATE_PARENT,
132 1, 2);
133 clks[ADSP_SC598_CLK_3PLL_PLLCLK] = clk_register_fixed_factor(NULL, "3pll_pllclk",
134 "3pll_vco",
135 CLK_SET_RATE_PARENT,
136 1, 2);
137
138 // Dividers from pll output
139 clks[ADSP_SC598_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk",
140 cgu0 + CGU_DIV, 0, 5, 0);
141 clks[ADSP_SC598_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk",
142 cgu0 + CGU_DIV, 8, 5, 0);
143 clks[ADSP_SC598_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk",
144 cgu0 + CGU_DIV, 16, 5, 0);
145 clks[ADSP_SC598_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk",
146 cgu0 + CGU_DIV, 22, 7, 0);
147 clks[ADSP_SC598_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0",
148 cgu0 + CGU_DIV, 5, 3, 0);
149 clks[ADSP_SC598_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0",
150 cgu0 + CGU_DIV, 13, 3, 0);
151 clks[ADSP_SC598_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv",
152 "cgu0_pllclk",
153 cgu0 + CGU_DIVEX, 16, 8, 0);
154 clks[ADSP_SC598_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel",
155 cgu0_s1sels, 2,
156 CLK_SET_RATE_PARENT,
157 cgu0 + CGU_CTL, 17, 1, 0);
158 clks[ADSP_SC598_CLK_CGU0_CCLK2] = clk_register_fixed_factor(NULL, "cclk2_0",
159 "cgu0_vco",
160 CLK_SET_RATE_PARENT,
161 1, 3);
162
163 clks[ADSP_SC598_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk",
164 cgu1 + CGU_DIV, 0, 5, 0);
165 clks[ADSP_SC598_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk",
166 cgu1 + CGU_DIV, 8, 5, 0);
167 clks[ADSP_SC598_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk",
168 cgu1 + CGU_DIV, 16, 5, 0);
169 clks[ADSP_SC598_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk",
170 cgu1 + CGU_DIV, 22, 7, 0);
171 clks[ADSP_SC598_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1",
172 cgu1 + CGU_DIV, 5, 3, 0);
173 clks[ADSP_SC598_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1",
174 cgu1 + CGU_DIV, 13, 3, 0);
175 clks[ADSP_SC598_CLK_CGU1_S0SELEXDIV] = cgu_divider("cgu1_s0selexdiv",
176 "cgu1_pllclk",
177 cgu1 + CGU_DIVEX, 0, 8, 0);
178 clks[ADSP_SC598_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv",
179 "cgu1_pllclk",
180 cgu1 + CGU_DIVEX, 16, 8, 0);
181 clks[ADSP_SC598_CLK_CGU1_S0SEL] = clk_register_mux(NULL, "cgu1_sclk0sel",
182 cgu1_s0sels, 2,
183 CLK_SET_RATE_PARENT,
184 cgu1 + CGU_CTL, 16, 1, 0);
185 clks[ADSP_SC598_CLK_CGU1_S1SEL] = clk_register_mux(NULL, "cgu1_sclk1sel",
186 cgu1_s1sels, 2,
187 CLK_SET_RATE_PARENT,
188 cgu1 + CGU_CTL, 17, 1, 0);
189 clks[ADSP_SC598_CLK_CGU1_CCLK2] = clk_register_fixed_factor(NULL, "cclk2_1",
190 "cgu1_vco",
191 CLK_SET_RATE_PARENT,
192 1, 3);
193
194 clks[ADSP_SC598_CLK_3PLL_DDIV] = clk_register_divider(NULL, "3pll_ddiv",
195 "3pll_pllclk",
196 CLK_SET_RATE_PARENT, pll3,
197 12, 5, 0);
198
199 // Gates to enable CGU outputs
200 clks[ADSP_SC598_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv",
201 cgu0 + CGU_CCBF_DIS, 0);
202 clks[ADSP_SC598_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv",
203 cgu0 + CGU_SCBF_DIS, 3);
204 clks[ADSP_SC598_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv",
205 cgu0 + CGU_SCBF_DIS, 2);
206 clks[ADSP_SC598_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_sclk1sel",
207 cgu0 + CGU_SCBF_DIS, 1);
208 clks[ADSP_SC598_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv",
209 cgu0 + CGU_SCBF_DIS, 0);
210
211 clks[ADSP_SC598_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv",
212 cgu1 + CGU_CCBF_DIS, 0);
213 clks[ADSP_SC598_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv",
214 cgu1 + CGU_SCBF_DIS, 3);
215 clks[ADSP_SC598_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv",
216 cgu1 + CGU_SCBF_DIS, 2);
217 clks[ADSP_SC598_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_sclk1sel",
218 cgu1 + CGU_SCBF_DIS, 1);
219 clks[ADSP_SC598_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_sclk0sel",
220 cgu1 + CGU_SCBF_DIS, 0);
221
222 // Extra half rate clocks generated in the CDU
223 clks[ADSP_SC598_CLK_DCLK0_HALF] = clk_register_fixed_factor(NULL, "dclk_0_half",
224 "dclk_0",
225 CLK_SET_RATE_PARENT,
226 1, 2);
227 clks[ADSP_SC598_CLK_DCLK1_HALF] = clk_register_fixed_factor(NULL, "dclk_1_half",
228 "dclk_1",
229 CLK_SET_RATE_PARENT,
230 1, 2);
231 clks[ADSP_SC598_CLK_CGU1_SCLK1_HALF] = clk_register_fixed_factor(NULL,
232 "sclk1_1_half",
233 "sclk1_1",
234 CLK_SET_RATE_PARENT,
235 1, 2);
236
237 // CDU output muxes
238 clks[ADSP_SC598_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0,
239 sharc0_sels);
240 clks[ADSP_SC598_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1,
241 sharc1_sels);
242 clks[ADSP_SC598_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels);
243 clks[ADSP_SC598_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3,
244 cdu_ddr_sels);
245 clks[ADSP_SC598_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels);
246 clks[ADSP_SC598_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels);
247 clks[ADSP_SC598_CLK_SPI_SEL] = cdu_mux("spi_sel", cdu + CDU_CFG6, spi_sels);
248 clks[ADSP_SC598_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels);
249 clks[ADSP_SC598_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels);
250 clks[ADSP_SC598_CLK_LP_DDR_SEL] = cdu_mux("lp_ddr_sel", cdu + CDU_CFG9,
251 lp_ddr_sels);
252 clks[ADSP_SC598_CLK_OSPI_REFCLK_SEL] = cdu_mux("ospi_refclk_sel", cdu + CDU_CFG10,
253 ospi_refclk_sels);
254 clks[ADSP_SC598_CLK_TRACE_SEL] = cdu_mux("trace_sel", cdu + CDU_CFG12,
255 trace_sels);
256 clks[ADSP_SC598_CLK_EMMC_SEL] = cdu_mux("emmc_sel", cdu + CDU_CFG13, emmc_sels);
257 clks[ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL] = cdu_mux("emmc_timer_qmc_sel",
258 cdu + CDU_CFG14,
259 emmc_timer_sels);
260
261 // CDU output enable gates
262 clks[ADSP_SC598_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0,
263 CLK_IS_CRITICAL);
264 clks[ADSP_SC598_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1,
265 CLK_IS_CRITICAL);
266 clks[ADSP_SC598_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2,
267 CLK_IS_CRITICAL);
268 clks[ADSP_SC598_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3,
269 0);
270 clks[ADSP_SC598_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0);
271 clks[ADSP_SC598_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0);
272 clks[ADSP_SC598_CLK_SPI] = cdu_gate("spi", "spi_sel", cdu + CDU_CFG6, 0);
273 clks[ADSP_SC598_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0);
274 clks[ADSP_SC598_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0);
275 clks[ADSP_SC598_CLK_LP_DDR] = cdu_gate("lp_ddr", "lp_ddr_sel", cdu + CDU_CFG9, 0);
276 clks[ADSP_SC598_CLK_OSPI_REFCLK] = cdu_gate("ospi_refclk", "ospi_refclk_sel",
277 cdu + CDU_CFG10, 0);
278 clks[ADSP_SC598_CLK_TRACE] = cdu_gate("trace", "trace_sel", cdu + CDU_CFG12, 0);
279 clks[ADSP_SC598_CLK_EMMC] = cdu_gate("emmc", "emmc_sel", cdu + CDU_CFG13, 0);
280 clks[ADSP_SC598_CLK_EMMC_TIMER_QMC] = cdu_gate("emmc_timer_qmc",
281 "emmc_timer_qmc_sel",
282 cdu + CDU_CFG14, 0);
283
284 // Dedicated DDR output mux
285 clks[ADSP_SC598_CLK_DDR] = clk_register_mux(NULL, "ddr", ddr_sels, 2,
286 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
287 pll3, 11, 1, 0);
288
289 ret = cdu_check_clocks(clks, ARRAY_SIZE(clks));
290 if (ret)
291 pr_err("CDU error detected\n");
292
293 return ret;
294}
295
296static const struct udevice_id adi_sc598_clk_ids[] = {
297 { .compatible = "adi,sc598-clocks" },
298 { },
299};
300
301U_BOOT_DRIVER(adi_sc598_clk) = {
302 .name = "clk_adi_sc598",
303 .id = UCLASS_CLK,
304 .of_match = adi_sc598_clk_ids,
305 .ops = &adi_clk_ops,
306 .probe = sc598_clock_probe,
307 .flags = DM_FLAG_PRE_RELOC,
308};