developer | f596c1a | 2023-07-19 17:17:49 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2022 MediaTek Inc. |
| 4 | * Author: Sam Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #include <fdtdec.h> |
| 8 | #include <init.h> |
| 9 | #include <asm/armv8/mmu.h> |
| 10 | #include <asm/global_data.h> |
developer | f596c1a | 2023-07-19 17:17:49 +0800 | [diff] [blame] | 11 | #include <asm/system.h> |
| 12 | |
| 13 | DECLARE_GLOBAL_DATA_PTR; |
| 14 | |
| 15 | #define SZ_8G _AC(0x200000000, ULL) |
| 16 | |
| 17 | int dram_init(void) |
| 18 | { |
| 19 | int ret; |
| 20 | |
| 21 | ret = fdtdec_setup_mem_size_base(); |
| 22 | if (ret) |
| 23 | return ret; |
| 24 | |
| 25 | gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G); |
| 26 | |
| 27 | return 0; |
| 28 | } |
| 29 | |
| 30 | int dram_init_banksize(void) |
| 31 | { |
| 32 | gd->bd->bi_dram[0].start = gd->ram_base; |
| 33 | gd->bd->bi_dram[0].size = gd->ram_size; |
| 34 | |
| 35 | return 0; |
| 36 | } |
| 37 | |
| 38 | void reset_cpu(ulong addr) |
| 39 | { |
| 40 | psci_system_reset(); |
| 41 | } |
| 42 | |
| 43 | static struct mm_region mt7988_mem_map[] = { |
| 44 | { |
| 45 | /* DDR */ |
| 46 | .virt = 0x40000000UL, |
| 47 | .phys = 0x40000000UL, |
| 48 | .size = 0x200000000ULL, |
| 49 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, |
| 50 | }, { |
| 51 | .virt = 0x00000000UL, |
| 52 | .phys = 0x00000000UL, |
| 53 | .size = 0x40000000UL, |
| 54 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 55 | PTE_BLOCK_NON_SHARE | |
| 56 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 57 | }, { |
| 58 | 0, |
| 59 | } |
| 60 | }; |
| 61 | |
| 62 | struct mm_region *mem_map = mt7988_mem_map; |