blob: 06653b5a8765922d4efde12cd40d7e52868526f7 [file] [log] [blame]
Sean Andersonedc32ab2020-06-24 06:41:25 -04001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
4 */
5
Tom Riniabb9a042024-05-18 20:20:43 -06006#include <common.h>
Sean Andersonedc32ab2020-06-24 06:41:25 -04007#include <clk.h>
8#include <dm.h>
9#include <fdt_support.h>
10#include <asm/io.h>
11
12phys_size_t get_effective_memsize(void)
13{
Tom Rinibb4dd962022-11-16 13:10:37 -050014 return CFG_SYS_SDRAM_SIZE;
Sean Andersonedc32ab2020-06-24 06:41:25 -040015}
16
Sean Anderson628b5dc2021-04-08 22:13:10 -040017static int sram_init(void)
Sean Andersonedc32ab2020-06-24 06:41:25 -040018{
19 int ret, i;
Sean Anderson7be6d2b2021-04-08 22:13:11 -040020 const char * const banks[] = { "sram0", "sram1", "aisram" };
Sean Andersonedc32ab2020-06-24 06:41:25 -040021 ofnode memory;
22 struct clk clk;
23
24 /* Enable RAM clocks */
Damien Le Moal6e5a8b72022-03-01 10:35:39 +000025 memory = ofnode_by_compatible(ofnode_null(), "canaan,k210-sram");
Sean Andersonedc32ab2020-06-24 06:41:25 -040026 if (ofnode_equal(memory, ofnode_null()))
27 return -ENOENT;
28
29 for (i = 0; i < ARRAY_SIZE(banks); i++) {
30 ret = clk_get_by_name_nodev(memory, banks[i], &clk);
31 if (ret)
32 continue;
33
34 ret = clk_enable(&clk);
Sean Andersonedc32ab2020-06-24 06:41:25 -040035 if (ret)
36 return ret;
37 }
38
Sean Anderson628b5dc2021-04-08 22:13:10 -040039 return 0;
40}
41
42int board_early_init_f(void)
43{
44 return sram_init();
45}
46
47int board_init(void)
48{
Sean Andersonedc32ab2020-06-24 06:41:25 -040049 return 0;
50}