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git01.mediatek.com / filogic / uboot / debed638ac9b038dfc248fd191c6baec5649f313 / . / arch / arm / dts / k3-am64-main.dtsi
blob: c5af2ffb8ee146d400276bc714fde953fb0955b0 [file] [log] [blame]
Dave Gerlachbb3c1672021-04-23 11:27:44 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM642 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_main {
9 oc_sram: sram@70000000 {
10 compatible = "mmio-sram";
11 reg = <0x00 0x70000000 0x00 0x200000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x00 0x70000000 0x200000>;
15
Aswath Govindraju39a68e72021-06-16 22:08:20 +0530[diff] [blame]16 tfa-sram@1c0000 {
17 reg = <0x1c0000 0x20000>;
Dave Gerlachbb3c1672021-04-23 11:27:44 -0500[diff] [blame]18 };
Aswath Govindrajudebed632021-06-16 22:08:21 +0530[diff] [blame^]19
20 dmsc-sram@1e0000 {
21 reg = <0x1e0000 0x1c000>;
22 };
23
24 sproxy-sram@1fc000 {
25 reg = <0x1fc000 0x4000>;
26 };
Dave Gerlachbb3c1672021-04-23 11:27:44 -0500[diff] [blame]27 };
28
29 gic500: interrupt-controller@1800000 {
30 compatible = "arm,gic-v3";
31 #address-cells = <2>;
32 #size-cells = <2>;
33 ranges;
34 #interrupt-cells = <3>;
35 interrupt-controller;
36 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
37 <0x00 0x01840000 0x00 0xC0000>; /* GICR */
38 /*
39 * vcpumntirq:
40 * virtual CPU interface maintenance interrupt
41 */
42 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
43
44 gic_its: msi-controller@1820000 {
45 compatible = "arm,gic-v3-its";
46 reg = <0x00 0x01820000 0x00 0x10000>;
47 socionext,synquacer-pre-its = <0x1000000 0x400000>;
48 msi-controller;
49 #msi-cells = <1>;
50 };
51 };
52
53 dmss: dmss {
54 compatible = "simple-mfd";
55 #address-cells = <2>;
56 #size-cells = <2>;
57 dma-ranges;
58 ranges;
59
60 ti,sci-dev-id = <25>;
61
62 secure_proxy_main: mailbox@4d000000 {
63 compatible = "ti,am654-secure-proxy";
64 #mbox-cells = <1>;
65 reg-names = "target_data", "rt", "scfg";
66 reg = <0x00 0x4d000000 0x00 0x80000>,
67 <0x00 0x4a600000 0x00 0x80000>,
68 <0x00 0x4a400000 0x00 0x80000>;
69 interrupt-names = "rx_012";
70 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
71 };
72
73 inta_main_dmss: interrupt-controller@48000000 {
74 compatible = "ti,sci-inta";
75 reg = <0x00 0x48000000 0x00 0x100000>;
76 #interrupt-cells = <0>;
77 interrupt-controller;
78 interrupt-parent = <&gic500>;
79 msi-controller;
80 ti,sci = <&dmsc>;
81 ti,sci-dev-id = <28>;
82 ti,interrupt-ranges = <4 68 36>;
83 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
84 };
85
86 main_bcdma: dma-controller@485c0100 {
87 compatible = "ti,am64-dmss-bcdma";
88 reg = <0x00 0x485c0100 0x00 0x100>,
89 <0x00 0x4c000000 0x00 0x20000>,
90 <0x00 0x4a820000 0x00 0x20000>,
91 <0x00 0x4aa40000 0x00 0x20000>,
92 <0x00 0x4bc00000 0x00 0x100000>;
93 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
94 msi-parent = <&inta_main_dmss>;
95 #dma-cells = <3>;
96
97 ti,sci = <&dmsc>;
98 ti,sci-dev-id = <26>;
99 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
100 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
101 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
102 };
103
104 main_pktdma: dma-controller@485c0000 {
105 compatible = "ti,am64-dmss-pktdma";
106 reg = <0x00 0x485c0000 0x00 0x100>,
107 <0x00 0x4a800000 0x00 0x20000>,
108 <0x00 0x4aa00000 0x00 0x40000>,
109 <0x00 0x4b800000 0x00 0x400000>;
110 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
111 msi-parent = <&inta_main_dmss>;
112 #dma-cells = <2>;
113
114 ti,sci = <&dmsc>;
115 ti,sci-dev-id = <30>;
116 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
117 <0x24>, /* CPSW_TX_CHAN */
118 <0x25>, /* SAUL_TX_0_CHAN */
119 <0x26>, /* SAUL_TX_1_CHAN */
120 <0x27>, /* ICSSG_0_TX_CHAN */
121 <0x28>; /* ICSSG_1_TX_CHAN */
122 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
123 <0x11>, /* RING_CPSW_TX_CHAN */
124 <0x12>, /* RING_SAUL_TX_0_CHAN */
125 <0x13>, /* RING_SAUL_TX_1_CHAN */
126 <0x14>, /* RING_ICSSG_0_TX_CHAN */
127 <0x15>; /* RING_ICSSG_1_TX_CHAN */
128 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
129 <0x2b>, /* CPSW_RX_CHAN */
130 <0x2d>, /* SAUL_RX_0_CHAN */
131 <0x2f>, /* SAUL_RX_1_CHAN */
132 <0x31>, /* SAUL_RX_2_CHAN */
133 <0x33>, /* SAUL_RX_3_CHAN */
134 <0x35>, /* ICSSG_0_RX_CHAN */
135 <0x37>; /* ICSSG_1_RX_CHAN */
136 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
137 <0x2c>, /* FLOW_CPSW_RX_CHAN */
138 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
139 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
140 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
141 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
142 };
143 };
144
145 dmsc: dmsc@44043000 {
146 compatible = "ti,k2g-sci";
147 ti,host-id = <12>;
148 mbox-names = "rx", "tx";
149 mboxes= <&secure_proxy_main 12>,
150 <&secure_proxy_main 13>;
151 reg-names = "debug_messages";
152 reg = <0x00 0x44043000 0x00 0xfe0>;
153
154 k3_pds: power-controller {
155 compatible = "ti,sci-pm-domain";
156 #power-domain-cells = <2>;
157 };
158
159 k3_clks: clocks {
160 compatible = "ti,k2g-sci-clk";
161 #clock-cells = <2>;
162 };
163
164 k3_reset: reset-controller {
165 compatible = "ti,sci-reset";
166 #reset-cells = <2>;
167 };
168 };
169
170 main_pmx0: pinctrl@f4000 {
171 compatible = "pinctrl-single";
172 reg = <0x00 0xf4000 0x00 0x2d0>;
173 #pinctrl-cells = <1>;
174 pinctrl-single,register-width = <32>;
175 pinctrl-single,function-mask = <0xffffffff>;
176 };
177
178 main_conf: syscon@43000000 {
179 compatible = "syscon", "simple-mfd";
180 reg = <0x00 0x43000000 0x00 0x20000>;
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges = <0x00 0x00 0x43000000 0x20000>;
184
185 chipid@14 {
186 compatible = "ti,am654-chipid";
187 reg = <0x00000014 0x4>;
188 };
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]189
190 phy_gmii_sel: phy@4044 {
191 compatible = "ti,am654-phy-gmii-sel";
192 reg = <0x4044 0x8>;
193 #phy-cells = <1>;
194 };
Dave Gerlachbb3c1672021-04-23 11:27:44 -0500[diff] [blame]195 };
196
197 main_uart0: serial@2800000 {
198 compatible = "ti,am64-uart", "ti,am654-uart";
199 reg = <0x00 0x02800000 0x00 0x100>;
200 reg-shift = <2>;
201 reg-io-width = <4>;
202 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
203 clock-frequency = <48000000>;
204 current-speed = <115200>;
205 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
206 clocks = <&k3_clks 146 0>;
207 clock-names = "fclk";
208 };
209
210 main_uart1: serial@2810000 {
211 compatible = "ti,am64-uart", "ti,am654-uart";
212 reg = <0x00 0x02810000 0x00 0x100>;
213 reg-shift = <2>;
214 reg-io-width = <4>;
215 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
216 clock-frequency = <48000000>;
217 current-speed = <115200>;
218 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
219 clocks = <&k3_clks 152 0>;
220 clock-names = "fclk";
221 };
222
223 main_uart2: serial@2820000 {
224 compatible = "ti,am64-uart", "ti,am654-uart";
225 reg = <0x00 0x02820000 0x00 0x100>;
226 reg-shift = <2>;
227 reg-io-width = <4>;
228 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
229 clock-frequency = <48000000>;
230 current-speed = <115200>;
231 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
232 clocks = <&k3_clks 153 0>;
233 clock-names = "fclk";
234 };
235
236 main_uart3: serial@2830000 {
237 compatible = "ti,am64-uart", "ti,am654-uart";
238 reg = <0x00 0x02830000 0x00 0x100>;
239 reg-shift = <2>;
240 reg-io-width = <4>;
241 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
242 clock-frequency = <48000000>;
243 current-speed = <115200>;
244 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
245 clocks = <&k3_clks 154 0>;
246 clock-names = "fclk";
247 };
248
249 main_uart4: serial@2840000 {
250 compatible = "ti,am64-uart", "ti,am654-uart";
251 reg = <0x00 0x02840000 0x00 0x100>;
252 reg-shift = <2>;
253 reg-io-width = <4>;
254 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
255 clock-frequency = <48000000>;
256 current-speed = <115200>;
257 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
258 clocks = <&k3_clks 155 0>;
259 clock-names = "fclk";
260 };
261
262 main_uart5: serial@2850000 {
263 compatible = "ti,am64-uart", "ti,am654-uart";
264 reg = <0x00 0x02850000 0x00 0x100>;
265 reg-shift = <2>;
266 reg-io-width = <4>;
267 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
268 clock-frequency = <48000000>;
269 current-speed = <115200>;
270 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
271 clocks = <&k3_clks 156 0>;
272 clock-names = "fclk";
273 };
274
275 main_uart6: serial@2860000 {
276 compatible = "ti,am64-uart", "ti,am654-uart";
277 reg = <0x00 0x02860000 0x00 0x100>;
278 reg-shift = <2>;
279 reg-io-width = <4>;
280 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
281 clock-frequency = <48000000>;
282 current-speed = <115200>;
283 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
284 clocks = <&k3_clks 158 0>;
285 clock-names = "fclk";
286 };
287
288 main_i2c0: i2c@20000000 {
289 compatible = "ti,am64-i2c", "ti,omap4-i2c";
290 reg = <0x00 0x20000000 0x00 0x100>;
291 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
295 clocks = <&k3_clks 102 2>;
296 clock-names = "fck";
297 };
298
299 main_i2c1: i2c@20010000 {
300 compatible = "ti,am64-i2c", "ti,omap4-i2c";
301 reg = <0x00 0x20010000 0x00 0x100>;
302 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
306 clocks = <&k3_clks 103 2>;
307 clock-names = "fck";
308 };
309
310 main_i2c2: i2c@20020000 {
311 compatible = "ti,am64-i2c", "ti,omap4-i2c";
312 reg = <0x00 0x20020000 0x00 0x100>;
313 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
317 clocks = <&k3_clks 104 2>;
318 clock-names = "fck";
319 };
320
321 main_i2c3: i2c@20030000 {
322 compatible = "ti,am64-i2c", "ti,omap4-i2c";
323 reg = <0x00 0x20030000 0x00 0x100>;
324 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
328 clocks = <&k3_clks 105 2>;
329 clock-names = "fck";
330 };
331
332 main_spi0: spi@20100000 {
333 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
334 reg = <0x00 0x20100000 0x00 0x400>;
335 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
339 clocks = <&k3_clks 141 0>;
340 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
341 dma-names = "tx0", "rx0";
342 };
343
344 main_spi1: spi@20110000 {
345 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
346 reg = <0x00 0x20110000 0x00 0x400>;
347 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
351 clocks = <&k3_clks 142 0>;
352 };
353
354 main_spi2: spi@20120000 {
355 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
356 reg = <0x00 0x20120000 0x00 0x400>;
357 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
361 clocks = <&k3_clks 143 0>;
362 };
363
364 main_spi3: spi@20130000 {
365 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
366 reg = <0x00 0x20130000 0x00 0x400>;
367 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
371 clocks = <&k3_clks 144 0>;
372 };
373
374 main_spi4: spi@20140000 {
375 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
376 reg = <0x00 0x20140000 0x00 0x400>;
377 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
381 clocks = <&k3_clks 145 0>;
382 };
383
384 sdhci0: mmc@fa10000 {
385 compatible = "ti,am64-sdhci-8bit";
386 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
387 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
388 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
389 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
390 clock-names = "clk_ahb", "clk_xin";
391 mmc-ddr-1_8v;
392 mmc-hs200-1_8v;
393 mmc-hs400-1_8v;
394 ti,trm-icp = <0x2>;
395 ti,otap-del-sel-legacy = <0x0>;
396 ti,otap-del-sel-mmc-hs = <0x0>;
397 ti,otap-del-sel-ddr52 = <0x6>;
398 ti,otap-del-sel-hs200 = <0x7>;
399 ti,otap-del-sel-hs400 = <0x4>;
400 };
401
402 sdhci1: mmc@fa00000 {
403 compatible = "ti,am64-sdhci-4bit";
404 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
405 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
406 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
407 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
408 clock-names = "clk_ahb", "clk_xin";
409 ti,trm-icp = <0x2>;
410 ti,otap-del-sel-legacy = <0x0>;
411 ti,otap-del-sel-sd-hs = <0xf>;
412 ti,otap-del-sel-sdr12 = <0xf>;
413 ti,otap-del-sel-sdr25 = <0xf>;
414 ti,otap-del-sel-sdr50 = <0xc>;
415 ti,otap-del-sel-sdr104 = <0x6>;
416 ti,otap-del-sel-ddr50 = <0x9>;
417 ti,clkbuf-sel = <0x7>;
418 };
Nishanth Menonc66f3a42021-05-04 18:00:54 -0500[diff] [blame]419
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]420 cpsw3g: ethernet@8000000 {
421 compatible = "ti,am642-cpsw-nuss";
422 #address-cells = <2>;
423 #size-cells = <2>;
424 reg = <0x0 0x8000000 0x0 0x200000>;
425 reg-names = "cpsw_nuss";
426 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
427 clocks = <&k3_clks 13 0>;
428 assigned-clocks = <&k3_clks 13 1>;
429 assigned-clock-parents = <&k3_clks 13 9>;
430 clock-names = "fck";
431 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
432
433 dmas = <&main_pktdma 0xC500 15>,
434 <&main_pktdma 0xC501 15>,
435 <&main_pktdma 0xC502 15>,
436 <&main_pktdma 0xC503 15>,
437 <&main_pktdma 0xC504 15>,
438 <&main_pktdma 0xC505 15>,
439 <&main_pktdma 0xC506 15>,
440 <&main_pktdma 0xC507 15>,
441 <&main_pktdma 0x4500 15>;
442 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
443 "tx7", "rx";
444
445 ethernet-ports {
446 #address-cells = <1>;
447 #size-cells = <0>;
448
449 cpsw_port1: port@1 {
450 reg = <1>;
451 ti,mac-only;
452 label = "port1";
453 phys = <&phy_gmii_sel 1>;
454 mac-address = [00 00 de ad be ef];
455 };
456
457 cpsw_port2: port@2 {
458 reg = <2>;
459 ti,mac-only;
460 label = "port2";
461 phys = <&phy_gmii_sel 2>;
462 mac-address = [00 01 de ad be ef];
463 };
464 };
465
466 cpsw3g_mdio: mdio@f00 {
467 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
468 reg = <0x0 0xf00 0x0 0x100>;
469 #address-cells = <1>;
470 #size-cells = <0>;
471 clocks = <&k3_clks 13 0>;
472 clock-names = "fck";
473 bus_freq = <1000000>;
474 };
475
476 cpts@3d000 {
477 compatible = "ti,j721e-cpts";
478 reg = <0x0 0x3d000 0x0 0x400>;
479 clocks = <&k3_clks 13 1>;
480 clock-names = "cpts";
481 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-names = "cpts";
483 ti,cpts-ext-ts-inputs = <4>;
484 ti,cpts-periodic-outputs = <2>;
485 };
486 };
487
Nishanth Menonc66f3a42021-05-04 18:00:54 -0500[diff] [blame]488 main_gpio0: gpio@600000 {
489 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
490 reg = <0x00 0x00600000 0x00 0x100>;
491 gpio-controller;
492 #gpio-cells = <2>;
493 interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
494 <77 1 IRQ_TYPE_EDGE_RISING>,
495 <77 2 IRQ_TYPE_EDGE_RISING>,
496 <77 3 IRQ_TYPE_EDGE_RISING>,
497 <77 4 IRQ_TYPE_EDGE_RISING>,
498 <77 5 IRQ_TYPE_EDGE_RISING>,
499 <77 6 IRQ_TYPE_EDGE_RISING>,
500 <77 7 IRQ_TYPE_EDGE_RISING>;
501 interrupt-controller;
502 #interrupt-cells = <2>;
503 ti,ngpio = <69>;
504 ti,davinci-gpio-unbanked = <0>;
505 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
506 clocks = <&k3_clks 77 0>;
507 clock-names = "gpio";
508 };
509
Aswath Govindraju308bd192021-06-04 22:00:35 +0530[diff] [blame]510 usbss0: cdns-usb@f900000{
511 compatible = "ti,am64-usb", "ti,j721e-usb";
512 reg = <0x00 0xf900000 0x00 0x100>;
513 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
514 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
515 clock-names = "ref", "lpm";
516 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
517 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
518 #address-cells = <2>;
519 #size-cells = <2>;
520 ranges;
521 usb0: usb@f400000{
522 compatible = "cdns,usb3";
523 reg = <0x00 0xf400000 0x00 0x10000>,
524 <0x00 0xf410000 0x00 0x10000>,
525 <0x00 0xf420000 0x00 0x10000>;
526 reg-names = "otg",
527 "xhci",
528 "dev";
529 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
530 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
531 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
532 interrupt-names = "host",
533 "peripheral",
534 "otg";
535 maximum-speed = "super-speed";
536 dr_mode = "otg";
537 };
538 };
539
Nishanth Menonc66f3a42021-05-04 18:00:54 -0500[diff] [blame]540 main_gpio1: gpio@601000 {
541 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
542 reg = <0x00 0x00601000 0x00 0x100>;
543 gpio-controller;
544 #gpio-cells = <2>;
545 interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
546 <78 1 IRQ_TYPE_EDGE_RISING>,
547 <78 2 IRQ_TYPE_EDGE_RISING>,
548 <78 3 IRQ_TYPE_EDGE_RISING>,
549 <78 4 IRQ_TYPE_EDGE_RISING>,
550 <78 5 IRQ_TYPE_EDGE_RISING>,
551 <78 6 IRQ_TYPE_EDGE_RISING>,
552 <78 7 IRQ_TYPE_EDGE_RISING>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 ti,ngpio = <69>;
556 ti,davinci-gpio-unbanked = <0>;
557 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
558 clocks = <&k3_clks 78 0>;
559 clock-names = "gpio";
560 };
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]561
562 main_i2c0: i2c@20000000 {
563 compatible = "ti,am64-i2c", "ti,omap4-i2c";
564 reg = <0x0 0x20000000 0x0 0x100>;
565 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 clock-names = "fck";
569 clocks = <&k3_clks 102 2>;
570 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
571 };
572
573 main_i2c1: i2c@20010000 {
574 compatible = "ti,am64-i2c", "ti,omap4-i2c";
575 reg = <0x0 0x20010000 0x0 0x100>;
576 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
577 #address-cells = <1>;
578 #size-cells = <0>;
579 clock-names = "fck";
580 clocks = <&k3_clks 103 2>;
581 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
582 };
583
584 main_i2c2: i2c@20020000 {
585 compatible = "ti,am64-i2c", "ti,omap4-i2c";
586 reg = <0x00 0x20020000 0x0 0x100>;
587 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
588 #address-cells = <1>;
589 #size-cells = <0>;
590 clock-names = "fck";
591 clocks = <&k3_clks 104 2>;
592 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
593 };
594
595 main_i2c3: i2c@20030000 {
596 compatible = "ti,am64-i2c", "ti,omap4-i2c";
597 reg = <0x00 0x20030000 0x0 0x100>;
598 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
599 #address-cells = <1>;
600 #size-cells = <0>;
601 clock-names = "fck";
602 clocks = <&k3_clks 105 2>;
603 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
604 };
Dave Gerlachbb3c1672021-04-23 11:27:44 -0500[diff] [blame]605};