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git01.mediatek.com / filogic / uboot / debdf8abb1e3df4246221543dd79469a82121c1e / . / configs / orangepi-r1-plus-lts-rk3328_defconfig
blob: 18dcf6cd4fa6cf9bfee8a87a6e0b51cb58dd753e [file] [log] [blame]
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_SKIP_LOWLEVEL_INIT=y
3CONFIG_COUNTER_FREQUENCY=24000000
4CONFIG_ARCH_ROCKCHIP=y
5CONFIG_TEXT_BASE=0x00200000
6CONFIG_SPL_GPIO=y
7CONFIG_NR_DRAM_BANKS=1
8CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
9CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
Tom Rini278f0f12023-08-07 15:17:12 -0400[diff] [blame]10CONFIG_SF_DEFAULT_SPEED=20000000
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]11CONFIG_ENV_OFFSET=0x3F8000
12CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
13CONFIG_DM_RESET=y
14CONFIG_ROCKCHIP_RK3328=y
15CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
Jonas Karlmandebdf8a2024-02-17 00:22:41 +0000[diff] [blame^]16CONFIG_ROCKCHIP_SPI_IMAGE=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]17CONFIG_TPL_LIBCOMMON_SUPPORT=y
18CONFIG_TPL_LIBGENERIC_SUPPORT=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]19CONFIG_SPL_STACK_R_ADDR=0x600000
20CONFIG_SPL_STACK=0x400000
21CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
22CONFIG_DEBUG_UART_BASE=0xFF130000
23CONFIG_DEBUG_UART_CLOCK=24000000
Jonas Karlmandebdf8a2024-02-17 00:22:41 +0000[diff] [blame^]24CONFIG_SPL_SPI_FLASH_SUPPORT=y
25CONFIG_SPL_SPI=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]26CONFIG_SYS_LOAD_ADDR=0x800800
27CONFIG_DEBUG_UART=y
28# CONFIG_ANDROID_BOOT_IMAGE is not set
29CONFIG_FIT=y
30CONFIG_FIT_VERBOSE=y
Jonas Karlmandc23df72024-02-17 00:22:33 +0000[diff] [blame]31CONFIG_SPL_FIT_SIGNATURE=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]32CONFIG_SPL_LOAD_FIT=y
Jonas Karlmandc23df72024-02-17 00:22:33 +0000[diff] [blame]33CONFIG_LEGACY_IMAGE_FORMAT=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]34CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
35# CONFIG_DISPLAY_CPUINFO is not set
36CONFIG_DISPLAY_BOARDINFO_LATE=y
37CONFIG_MISC_INIT_R=y
38CONFIG_SPL_MAX_SIZE=0x40000
39CONFIG_SPL_PAD_TO=0x7f8000
40CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
41CONFIG_SPL_BSS_START_ADDR=0x2000000
42CONFIG_SPL_BSS_MAX_SIZE=0x2000
43# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
44# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
45CONFIG_SPL_STACK_R=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]46CONFIG_SPL_POWER=y
Jonas Karlmandebdf8a2024-02-17 00:22:41 +0000[diff] [blame^]47CONFIG_SPL_SPI_LOAD=y
48CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]49CONFIG_SPL_ATF=y
50CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
51CONFIG_TPL_SYS_MALLOC_SIMPLE=y
52CONFIG_CMD_BOOTZ=y
Jonas Karlmandc23df72024-02-17 00:22:33 +0000[diff] [blame]53CONFIG_CMD_GPIO=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]54CONFIG_CMD_GPT=y
55CONFIG_CMD_MMC=y
56CONFIG_CMD_USB=y
57# CONFIG_CMD_SETEXPR is not set
58CONFIG_CMD_TIME=y
Jonas Karlmandc23df72024-02-17 00:22:33 +0000[diff] [blame]59CONFIG_CMD_REGULATOR=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]60CONFIG_SPL_OF_CONTROL=y
61CONFIG_TPL_OF_CONTROL=y
62CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
63CONFIG_TPL_OF_PLATDATA=y
64CONFIG_ENV_IS_IN_MMC=y
65CONFIG_SYS_RELOC_GD_ENV_ADDR=y
66CONFIG_SYS_MMC_ENV_DEV=1
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]67CONFIG_TPL_DM=y
Jonas Karlmandc23df72024-02-17 00:22:33 +0000[diff] [blame]68CONFIG_SPL_DM_SEQ_ALIAS=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]69CONFIG_REGMAP=y
70CONFIG_SPL_REGMAP=y
71CONFIG_TPL_REGMAP=y
72CONFIG_SYSCON=y
73CONFIG_SPL_SYSCON=y
74CONFIG_TPL_SYSCON=y
75CONFIG_CLK=y
76CONFIG_SPL_CLK=y
77CONFIG_FASTBOOT_BUF_ADDR=0x800800
78CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
79CONFIG_ROCKCHIP_GPIO=y
80CONFIG_SYS_I2C_ROCKCHIP=y
Jonas Karlmanac8d1572023-11-12 17:48:57 +0000[diff] [blame]81CONFIG_MISC=y
Jonas Karlmandc23df72024-02-17 00:22:33 +0000[diff] [blame]82CONFIG_ROCKCHIP_EFUSE=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]83CONFIG_MMC_DW=y
84CONFIG_MMC_DW_ROCKCHIP=y
Jonas Karlmandebdf8a2024-02-17 00:22:41 +0000[diff] [blame^]85CONFIG_SPI_FLASH_SFDP_SUPPORT=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]86CONFIG_SPI_FLASH_GIGADEVICE=y
Jonas Karlmandebdf8a2024-02-17 00:22:41 +0000[diff] [blame^]87CONFIG_SPI_FLASH_MACRONIX=y
88CONFIG_SPI_FLASH_WINBOND=y
89CONFIG_SPI_FLASH_XMC=y
90CONFIG_SPI_FLASH_ZBIT=y
Jonas Karlmandc23df72024-02-17 00:22:33 +0000[diff] [blame]91CONFIG_PHY_MOTORCOMM=y
92CONFIG_PHY_REALTEK=y
93CONFIG_DM_MDIO=y
94CONFIG_DM_ETH_PHY=y
95CONFIG_PHY_GIGE=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]96CONFIG_ETH_DESIGNWARE=y
97CONFIG_GMAC_ROCKCHIP=y
Jonas Karlmandc23df72024-02-17 00:22:33 +0000[diff] [blame]98CONFIG_PHY_ROCKCHIP_INNO_USB2=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]99CONFIG_PINCTRL=y
100CONFIG_SPL_PINCTRL=y
101CONFIG_DM_PMIC=y
102CONFIG_PMIC_RK8XX=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]103CONFIG_SPL_DM_REGULATOR=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]104CONFIG_DM_REGULATOR_FIXED=y
105CONFIG_SPL_DM_REGULATOR_FIXED=y
106CONFIG_REGULATOR_RK8XX=y
107CONFIG_PWM_ROCKCHIP=y
108CONFIG_RAM=y
109CONFIG_SPL_RAM=y
110CONFIG_TPL_RAM=y
Jonas Karlmandc23df72024-02-17 00:22:33 +0000[diff] [blame]111CONFIG_DM_RNG=y
112CONFIG_RNG_ROCKCHIP=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]113CONFIG_BAUDRATE=1500000
114CONFIG_DEBUG_UART_SHIFT=2
115CONFIG_SYS_NS16550_MEM32=y
116CONFIG_ROCKCHIP_SPI=y
117CONFIG_SYSINFO=y
118CONFIG_SYSRESET=y
119# CONFIG_TPL_SYSRESET is not set
120CONFIG_USB=y
121CONFIG_USB_XHCI_HCD=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]122CONFIG_USB_EHCI_HCD=y
123CONFIG_USB_EHCI_GENERIC=y
124CONFIG_USB_OHCI_HCD=y
125CONFIG_USB_OHCI_GENERIC=y
126CONFIG_USB_DWC2=y
127CONFIG_USB_DWC3=y
128# CONFIG_USB_DWC3_GADGET is not set
Jonas Karlmanac8d1572023-11-12 17:48:57 +0000[diff] [blame]129CONFIG_USB_DWC3_GENERIC=y
Tianling Shen0c8dea52023-05-20 19:20:50 +0800[diff] [blame]130CONFIG_USB_GADGET=y
131CONFIG_USB_GADGET_DWC2_OTG=y
132CONFIG_SPL_TINY_MEMSET=y
133CONFIG_TPL_TINY_MEMSET=y
134CONFIG_ERRNO_STR=y