| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Tom Warren | f80dd82 | 2015-02-02 13:22:29 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. |
| Tom Warren | f80dd82 | 2015-02-02 13:22:29 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _TEGRA210_MC_H_ |
| 7 | #define _TEGRA210_MC_H_ |
| 8 | |
| 9 | /** |
| 10 | * Defines the memory controller registers we need/care about |
| 11 | */ |
| 12 | struct mc_ctlr { |
| 13 | u32 reserved0[4]; /* offset 0x00 - 0x0C */ |
| 14 | u32 mc_smmu_config; /* offset 0x10 */ |
| 15 | u32 mc_smmu_tlb_config; /* offset 0x14 */ |
| 16 | u32 mc_smmu_ptc_config; /* offset 0x18 */ |
| 17 | u32 mc_smmu_ptb_asid; /* offset 0x1C */ |
| 18 | u32 mc_smmu_ptb_data; /* offset 0x20 */ |
| 19 | u32 reserved1[3]; /* offset 0x24 - 0x2C */ |
| 20 | u32 mc_smmu_tlb_flush; /* offset 0x30 */ |
| 21 | u32 mc_smmu_ptc_flush; /* offset 0x34 */ |
| 22 | u32 reserved2[6]; /* offset 0x38 - 0x4C */ |
| 23 | u32 mc_emem_cfg; /* offset 0x50 */ |
| 24 | u32 mc_emem_adr_cfg; /* offset 0x54 */ |
| 25 | u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ |
| 26 | u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ |
| 27 | u32 reserved3[4]; /* offset 0x60 - 0x6C */ |
| 28 | u32 mc_security_cfg0; /* offset 0x70 */ |
| 29 | u32 mc_security_cfg1; /* offset 0x74 */ |
| 30 | u32 reserved4[6]; /* offset 0x7C - 0x8C */ |
| 31 | u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ |
| 32 | u32 reserved5[74]; /* offset 0x100 - 0x224 */ |
| 33 | u32 mc_smmu_translation_enable_0; /* offset 0x228 */ |
| 34 | u32 mc_smmu_translation_enable_1; /* offset 0x22C */ |
| 35 | u32 mc_smmu_translation_enable_2; /* offset 0x230 */ |
| 36 | u32 mc_smmu_translation_enable_3; /* offset 0x234 */ |
| 37 | u32 mc_smmu_afi_asid; /* offset 0x238 */ |
| 38 | u32 mc_smmu_avpc_asid; /* offset 0x23C */ |
| 39 | u32 mc_smmu_dc_asid; /* offset 0x240 */ |
| 40 | u32 mc_smmu_dcb_asid; /* offset 0x244 */ |
| 41 | u32 reserved6[2]; /* offset 0x248 - 0x24C */ |
| 42 | u32 mc_smmu_hc_asid; /* offset 0x250 */ |
| 43 | u32 mc_smmu_hda_asid; /* offset 0x254 */ |
| 44 | u32 mc_smmu_isp2_asid; /* offset 0x258 */ |
| 45 | u32 reserved7[2]; /* offset 0x25C - 0x260 */ |
| 46 | u32 mc_smmu_msenc_asid; /* offset 0x264 */ |
| 47 | u32 mc_smmu_nv_asid; /* offset 0x268 */ |
| 48 | u32 mc_smmu_nv2_asid; /* offset 0x26C */ |
| 49 | u32 mc_smmu_ppcs_asid; /* offset 0x270 */ |
| 50 | u32 mc_smmu_sata_asid; /* offset 0x274 */ |
| 51 | u32 reserved8[1]; /* offset 0x278 */ |
| 52 | u32 mc_smmu_vde_asid; /* offset 0x27C */ |
| 53 | u32 mc_smmu_vi_asid; /* offset 0x280 */ |
| 54 | u32 mc_smmu_vic_asid; /* offset 0x284 */ |
| 55 | u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ |
| 56 | u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ |
| 57 | u32 reserved9[1]; /* offset 0x290 */ |
| 58 | u32 mc_smmu_tsec_asid; /* offset 0x294 */ |
| 59 | u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ |
| 60 | u32 reserved10[235]; /* offset 0x29C - 0x644 */ |
| 61 | u32 mc_video_protect_bom; /* offset 0x648 */ |
| 62 | u32 mc_video_protect_size_mb; /* offset 0x64c */ |
| 63 | u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ |
| 64 | }; |
| 65 | |
| 66 | #define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) |
| 67 | |
| 68 | #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) |
| 69 | #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) |
| 70 | |
| 71 | #endif /* _TEGRA210_MC_H_ */ |