| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 2 | /* |
| Patrice Chotard | 9e21624 | 2017-10-23 09:53:57 +0200 | [diff] [blame] | 3 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
| Patrice Chotard | 5d9950d | 2020-12-02 18:47:30 +0100 | [diff] [blame] | 4 | * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. |
| Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __STI_SDHCI_H__ |
| 8 | #define __STI_SDHCI_H__ |
| 9 | |
| Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 10 | #ifndef __ASSEMBLY__ |
| 11 | #include <linux/bitops.h> |
| 12 | #endif |
| 13 | |
| Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 14 | #define FLASHSS_MMC_CORE_CONFIG_1 0x400 |
| 15 | #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24) |
| 16 | #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12) |
| 17 | |
| 18 | #define STI_FLASHSS_MMC_CORE_CONFIG_1 \ |
| 19 | (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \ |
| 20 | FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN) |
| 21 | |
| 22 | #define FLASHSS_MMC_CORE_CONFIG_2 0x404 |
| 23 | #define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28) |
| 24 | #define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20) |
| 25 | #define MAX_BLK_LENGTH_1024 BIT(16) |
| 26 | #define BASE_CLK_FREQ_200 0xc8 |
| 27 | |
| 28 | #define STI_FLASHSS_MMC_CORE_CONFIG2 \ |
| 29 | (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ |
| 30 | FLASHSS_MMC_CORECFG_8BIT_EMMC | \ |
| 31 | MAX_BLK_LENGTH_1024 | \ |
| 32 | BASE_CLK_FREQ_200 << 0) |
| 33 | |
| 34 | #define STI_FLASHSS_SDCARD_CORE_CONFIG2 \ |
| 35 | (FLASHSS_MMC_CORECFG_HIGH_SPEED | \ |
| 36 | MAX_BLK_LENGTH_1024 | \ |
| 37 | BASE_CLK_FREQ_200) |
| 38 | |
| 39 | #define FLASHSS_MMC_CORE_CONFIG_3 0x408 |
| 40 | #define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28) |
| 41 | #define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20) |
| 42 | #define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8) |
| 43 | #define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4) |
| 44 | #define FLASHSS_MMC_CORECFG_SDMA BIT(0) |
| 45 | |
| 46 | #define STI_FLASHSS_MMC_CORE_CONFIG3 \ |
| 47 | (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \ |
| 48 | FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ |
| 49 | FLASHSS_MMC_CORECFG_3P3_VOLT | \ |
| 50 | FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ |
| 51 | FLASHSS_MMC_CORECFG_SDMA) |
| 52 | |
| 53 | #define STI_FLASHSS_SDCARD_CORE_CONFIG3 \ |
| 54 | (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \ |
| 55 | FLASHSS_MMC_CORECFG_3P3_VOLT | \ |
| 56 | FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \ |
| 57 | FLASHSS_MMC_CORECFG_SDMA) |
| 58 | |
| 59 | #define FLASHSS_MMC_CORE_CONFIG_4 0x40c |
| 60 | #define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20) |
| 61 | #define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16) |
| 62 | #define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12) |
| 63 | |
| 64 | #define STI_FLASHSS_MMC_CORE_CONFIG4 \ |
| 65 | (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \ |
| 66 | FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \ |
| 67 | FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT) |
| 68 | |
| 69 | #define ST_MMC_CCONFIG_REG_5 0x210 |
| 70 | #define SYSCONF_MMC1_ENABLE_BIT 3 |
| 71 | |
| 72 | #endif /* _STI_SDHCI_H_ */ |