| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries |
| 3 | %YAML 1.2 |
| 4 | --- |
| 5 | $id: http://devicetree.org/schemas/i2c/atmel,at91sam-i2c.yaml# |
| 6 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 7 | |
| 8 | title: I2C for Atmel/Microchip platforms |
| 9 | |
| 10 | maintainers: |
| 11 | - Alexandre Belloni <alexandre.belloni@bootlin.com> |
| 12 | |
| 13 | properties: |
| 14 | compatible: |
| 15 | oneOf: |
| 16 | - items: |
| 17 | - enum: |
| 18 | - atmel,at91rm9200-i2c |
| 19 | - atmel,at91sam9261-i2c |
| 20 | - atmel,at91sam9260-i2c |
| 21 | - atmel,at91sam9g20-i2c |
| 22 | - atmel,at91sam9g10-i2c |
| 23 | - atmel,at91sam9x5-i2c |
| 24 | - atmel,sama5d4-i2c |
| 25 | - atmel,sama5d2-i2c |
| 26 | - microchip,sam9x60-i2c |
| 27 | - items: |
| 28 | - const: microchip,sama7g5-i2c |
| 29 | - const: microchip,sam9x60-i2c |
| 30 | |
| 31 | reg: |
| 32 | maxItems: 1 |
| 33 | |
| 34 | interrupts: |
| 35 | maxItems: 1 |
| 36 | |
| 37 | "#address-cells": |
| 38 | const: 1 |
| 39 | |
| 40 | "#size-cells": |
| 41 | const: 0 |
| 42 | |
| 43 | clocks: |
| 44 | maxItems: 1 |
| 45 | |
| 46 | clock-frequency: |
| 47 | default: 100000 |
| 48 | |
| 49 | dmas: |
| 50 | items: |
| 51 | - description: TX DMA Channel Specifier |
| 52 | - description: RX DMA Channel Specifier |
| 53 | |
| 54 | dma-names: |
| 55 | items: |
| 56 | - const: tx |
| 57 | - const: rx |
| 58 | |
| 59 | atmel,fifo-size: |
| 60 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 61 | description: | |
| 62 | Maximum number of data the RX and TX FIFOs can store for |
| 63 | FIFO capable I2C controllers. |
| 64 | |
| 65 | scl-gpios: true |
| 66 | |
| 67 | sda-gpios: true |
| 68 | |
| 69 | required: |
| 70 | - compatible |
| 71 | - reg |
| 72 | - interrupts |
| 73 | - "#address-cells" |
| 74 | - "#size-cells" |
| 75 | - clocks |
| 76 | |
| 77 | allOf: |
| 78 | - $ref: i2c-controller.yaml |
| 79 | - if: |
| 80 | properties: |
| 81 | compatible: |
| 82 | contains: |
| 83 | enum: |
| 84 | - atmel,sama5d4-i2c |
| 85 | - atmel,sama5d2-i2c |
| 86 | - microchip,sam9x60-i2c |
| 87 | - microchip,sama7g5-i2c |
| 88 | then: |
| 89 | properties: |
| 90 | i2c-sda-hold-time-ns: |
| 91 | description: |
| 92 | TWD hold time |
| 93 | maxItems: 1 |
| 94 | |
| 95 | unevaluatedProperties: false |
| 96 | |
| 97 | examples: |
| 98 | - | |
| 99 | #include <dt-bindings/interrupt-controller/irq.h> |
| 100 | #include <dt-bindings/dma/at91.h> |
| 101 | #include <dt-bindings/gpio/gpio.h> |
| 102 | |
| 103 | i2c0: i2c@fff84000 { |
| 104 | compatible = "atmel,at91sam9g20-i2c"; |
| 105 | reg = <0xfff84000 0x100>; |
| 106 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; |
| 107 | #address-cells = <1>; |
| 108 | #size-cells = <0>; |
| 109 | clocks = <&twi0_clk>; |
| 110 | clock-frequency = <400000>; |
| 111 | |
| 112 | eeprom@50 { |
| 113 | compatible = "atmel,24c512"; |
| 114 | reg = <0x50>; |
| 115 | pagesize = <128>; |
| 116 | }; |
| 117 | }; |
| 118 | |
| 119 | i2c1: i2c@f8034600 { |
| 120 | compatible = "atmel,sama5d2-i2c"; |
| 121 | reg = <0xf8034600 0x100>; |
| 122 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; |
| 123 | dmas = <&dma0 |
| 124 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) |
| 125 | AT91_XDMAC_DT_PERID(11)>, |
| 126 | <&dma0 |
| 127 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) |
| 128 | AT91_XDMAC_DT_PERID(12)>; |
| 129 | dma-names = "tx", "rx"; |
| 130 | #address-cells = <1>; |
| 131 | #size-cells = <0>; |
| 132 | clocks = <&flx0>; |
| 133 | atmel,fifo-size = <16>; |
| 134 | i2c-sda-hold-time-ns = <336>; |
| 135 | pinctrl-names = "default", "gpio"; |
| 136 | pinctrl-0 = <&pinctrl_i2c0>; |
| 137 | pinctrl-1 = <&pinctrl_i2c0_gpio>; |
| 138 | sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; |
| 139 | scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 140 | |
| 141 | eeprom@54 { |
| 142 | compatible = "atmel,24c02"; |
| 143 | reg = <0x54>; |
| 144 | pagesize = <16>; |
| 145 | }; |
| 146 | }; |