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git01.mediatek.com / filogic / uboot / de70b47f44d775a800c998e3ddd00b79e8a16c28 / . / arch / arm / dts / imx8mp-verdin-wifi-dev-u-boot.dtsi
blob: 271d511518e4f91b7b7911255700c220565096f3 [file] [log] [blame]
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
9 firmware {
10 optee {
11 compatible = "linaro,optee-tz";
12 method = "smc";
13 };
14 };
15
16 wdt-reboot {
17 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]19 wdt = <&wdog1>;
20 };
21};
22
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]23&{/aliases} {
24 eeprom0 = &eeprom_module;
25 eeprom1 = &eeprom_carrier_board;
26 eeprom2 = &eeprom_display_adapter;
27};
28
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]29&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-all;
31 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]32 /delete-property/ assigned-clocks;
33 /delete-property/ assigned-clock-parents;
34 /delete-property/ assigned-clock-rates;
35
36};
37
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]38&crypto {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]40};
41
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]42&eqos {
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]43 /delete-property/ assigned-clocks;
44 /delete-property/ assigned-clock-parents;
45 /delete-property/ assigned-clock-rates;
46};
47
48&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]50};
51
52&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]54
55 regulator-ethphy {
56 gpio-hog;
57 gpios = <20 GPIO_ACTIVE_HIGH>;
58 line-name = "reg_ethphy";
59 output-high;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_reg_eth>;
62 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]63};
64
65&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]67};
68
69&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]71};
72
73&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]75};
76
77&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]79
80 eeprom_module: eeprom@50 {
81 compatible = "i2c-eeprom";
82 pagesize = <16>;
83 reg = <0x50>;
84 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]85};
86
87&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]89};
90
91&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]93};
94
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]95&i2c4 {
96 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
97 eeprom_display_adapter: eeprom@50 {
98 compatible = "i2c-eeprom";
99 pagesize = <16>;
100 reg = <0x50>;
101 };
102
103 /* EEPROM on carrier board */
104 eeprom_carrier_board: eeprom@57 {
105 compatible = "i2c-eeprom";
106 pagesize = <16>;
107 reg = <0x57>;
108 };
109};
110
111&pca9450 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]113};
114
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]115&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]117};
118
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]119&pinctrl_usdhc2_pwr_en {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]121 u-boot,off-on-delay-us = <20000>;
122};
123
124&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]126};
127
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]128&pinctrl_usdhc2_cd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]130};
131
132&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]133 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]134};
135
136&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]137 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]138};
139
140&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]141 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]142};
143
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]144&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]145 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]146};
147
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]148&sec_jr0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]149 bootph-pre-ram;
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]150};
151
152&sec_jr1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]153 bootph-pre-ram;
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]154};
155
156&sec_jr2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]157 bootph-pre-ram;
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]158};
159
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]160&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]161 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]162};
163
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]164&usdhc1 {
165 status = "disabled";
166};
167
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]168&usdhc2 {
169 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
170 assigned-clock-rates = <400000000>;
171 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
172 sd-uhs-ddr50;
173 sd-uhs-sdr104;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]174 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]175};
176
177&usdhc3 {
178 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
179 assigned-clock-rates = <400000000>;
180 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
181 mmc-hs400-1_8v;
182 mmc-hs400-enhanced-strobe;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]183 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]184};
185
186&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]187 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]188};