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Peng Fanc47e09d2019-12-30 17:46:21 +08001/*
2 * Copyright 2018-2019 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07008#include <cpu_func.h>
Simon Glassf11478f2019-12-28 10:45:07 -07009#include <hang.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080010#include <spl.h>
11#include <asm/io.h>
12#include <errno.h>
13#include <asm/io.h>
14#include <asm/mach-imx/iomux-v3.h>
15#include <asm/arch/imx8mp_pins.h>
16#include <asm/arch/sys_proto.h>
17#include <asm/mach-imx/boot_mode.h>
18#include <power/pmic.h>
19
20#include <power/pca9450.h>
21#include <asm/arch/clock.h>
22#include <asm/mach-imx/gpio.h>
23#include <asm/mach-imx/mxc_i2c.h>
24#include <fsl_esdhc.h>
25#include <mmc.h>
26#include <asm/arch/ddr.h>
27
28#include <dm/uclass.h>
29#include <dm/device.h>
30#include <dm/uclass-internal.h>
31#include <dm/device-internal.h>
32
33DECLARE_GLOBAL_DATA_PTR;
34
35int spl_board_boot_device(enum boot_device boot_dev_spl)
36{
37 return BOOT_DEVICE_BOOTROM;
38}
39
40void spl_dram_init(void)
41{
42 ddr_init(&dram_timing);
43}
44
45void spl_board_init(void)
46{
47 struct udevice *dev;
48 int ret;
49
50 puts("Normal Boot\n");
51
52 ret = uclass_get_device_by_name(UCLASS_CLK,
53 "clock-controller@30380000",
54 &dev);
55 if (ret < 0)
56 printf("Failed to find clock node. Check device tree\n");
57}
58
59#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
60#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
61struct i2c_pads_info i2c_pad_info1 = {
62 .scl = {
63 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
64 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
65 .gp = IMX_GPIO_NR(5, 14),
66 },
67 .sda = {
68 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
69 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
70 .gp = IMX_GPIO_NR(5, 15),
71 },
72};
73
74#ifdef CONFIG_POWER
75#define I2C_PMIC 0
76int power_init_board(void)
77{
78 struct pmic *p;
79 int ret;
80
81 ret = power_pca9450b_init(I2C_PMIC);
82 if (ret)
83 printf("power init failed");
84 p = pmic_get("PCA9450");
85 pmic_probe(p);
86
87 /* BUCKxOUT_DVS0/1 control BUCK123 output */
88 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
89
90 /*
91 * increase VDD_SOC to typical value 0.95V before first
92 * DRAM access, set DVS1 to 0.85v for suspend.
93 * Enable DVS control through PMIC_STBY_REQ and
94 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
95 */
96 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
97 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
98 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
99
100 /* set WDOG_B_CFG to cold reset */
101 pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
102
103 return 0;
104}
105#endif
106
107#ifdef CONFIG_SPL_LOAD_FIT
108int board_fit_config_name_match(const char *name)
109{
110 /* Just empty function now - can't decide what to choose */
111 debug("%s: %s\n", __func__, name);
112
113 return 0;
114}
115#endif
116
117void board_init_f(ulong dummy)
118{
119 int ret;
120
121 arch_cpu_init();
122
123 init_uart_clk(1);
124
125 board_early_init_f();
126
127 timer_init();
128
129 preloader_console_init();
130
131 /* Clear the BSS. */
132 memset(__bss_start, 0, __bss_end - __bss_start);
133
134 ret = spl_init();
135 if (ret) {
136 debug("spl_init() failed: %d\n", ret);
137 hang();
138 }
139
140 enable_tzc380();
141
Peng Fanc47e09d2019-12-30 17:46:21 +0800142 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
143
144 power_init_board();
145
146 /* DDR initialization */
147 spl_dram_init();
148
149 board_init_r(NULL, 0);
150}