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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
goda.yusukefd768072008-01-25 20:46:36 +09002/*
3 * Configuation settings for the Renesas Solutions Migo-R board
4 *
5 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
goda.yusukefd768072008-01-25 20:46:36 +09006 */
7
8#ifndef __MIGO_R_H
9#define __MIGO_R_H
10
goda.yusukefd768072008-01-25 20:46:36 +090011#define CONFIG_CPU_SH7722 1
goda.yusukefd768072008-01-25 20:46:36 +090012
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020013#define CONFIG_DISPLAY_BOARDINFO
goda.yusukefd768072008-01-25 20:46:36 +090014
15/* SMC9111 */
Ben Warren0fd6aae2009-10-04 22:37:03 -070016#define CONFIG_SMC91111
goda.yusukefd768072008-01-25 20:46:36 +090017#define CONFIG_SMC91111_BASE (0xB0000000)
18
19/* MEMORY */
20#define MIGO_R_SDRAM_BASE (0x8C000000)
21#define MIGO_R_FLASH_BASE_1 (0xA0000000)
22#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
23
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020024#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
goda.yusukefd768072008-01-25 20:46:36 +090026
27/* SCIF */
goda.yusukefd768072008-01-25 20:46:36 +090028#define CONFIG_CONS_SCIF0 1
goda.yusukefd768072008-01-25 20:46:36 +090029
goda.yusukefd768072008-01-25 20:46:36 +090030/* Enable alternate, more extensive, memory test */
goda.yusukefd768072008-01-25 20:46:36 +090031/* Scratch address used by the alternate memory test */
goda.yusukefd768072008-01-25 20:46:36 +090032
33/* Enable temporary baudrate change while serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034#undef CONFIG_SYS_LOADS_BAUD_CHANGE
goda.yusukefd768072008-01-25 20:46:36 +090035
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020036#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE)
goda.yusukefd768072008-01-25 20:46:36 +090037/* maybe more, but if so u-boot doesn't know about it... */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090039/* default load address for scripts ?!? */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090041
42/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
goda.yusukefd768072008-01-25 20:46:36 +090044/* Monitor size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090046/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020047#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020048#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090049
50/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051#undef CONFIG_SYS_FLASH_QUIET_TEST
goda.yusukefd768072008-01-25 20:46:36 +090052/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_FLASH_EMPTY_INFO
goda.yusukefd768072008-01-25 20:46:36 +090054/* Physical start address of Flash memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020055#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1)
goda.yusukefd768072008-01-25 20:46:36 +090056/* Max number of sectors on each Flash chip */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#define CONFIG_SYS_MAX_FLASH_SECT 512
goda.yusukefd768072008-01-25 20:46:36 +090058
59/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_MAX_FLASH_BANKS 1
61#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
goda.yusukefd768072008-01-25 20:46:36 +090062
63/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +090065/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020066#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +090067/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +090069/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +090071
72/* Use hardware flash sectors protection instead of U-Boot software protection */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#undef CONFIG_SYS_DIRECT_FLASH_TFTP
goda.yusukefd768072008-01-25 20:46:36 +090074
75/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
goda.yusukefd768072008-01-25 20:46:36 +090077
78/* Board Clock */
79#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090080#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
goda.yusukefd768072008-01-25 20:46:36 +090081
82#endif /* __MIGO_R_H */