Thomas Chou | fb798b1 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 1 | menu "Timer Support" |
| 2 | |
| 3 | config TIMER |
Bin Meng | 8a7b864 | 2015-11-13 00:11:14 -0800 | [diff] [blame] | 4 | bool "Enable driver model for timer drivers" |
Thomas Chou | fb798b1 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 5 | depends on DM |
| 6 | help |
Bin Meng | 8a7b864 | 2015-11-13 00:11:14 -0800 | [diff] [blame] | 7 | Enable driver model for timer access. It uses the same API as |
| 8 | lib/time.c, but now implemented by the uclass. The first timer |
Thomas Chou | fb798b1 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 9 | will be used. The timer is usually a 32 bits free-running up |
| 10 | counter. There may be no real tick, and no timer interrupt. |
| 11 | |
Philipp Tomsich | 4fac4ea | 2017-07-28 17:38:42 +0200 | [diff] [blame] | 12 | config SPL_TIMER |
| 13 | bool "Enable driver model for timer drivers in SPL" |
| 14 | depends on TIMER && SPL |
| 15 | help |
| 16 | Enable support for timer drivers in SPL. These can be used to get |
| 17 | a timer value when in SPL, or perhaps for implementing a delay |
| 18 | function. This enables the drivers in drivers/timer as part of an |
| 19 | SPL build. |
| 20 | |
| 21 | config TPL_TIMER |
| 22 | bool "Enable driver model for timer drivers in TPL" |
| 23 | depends on TIMER && TPL |
| 24 | help |
| 25 | Enable support for timer drivers in TPL. These can be used to get |
| 26 | a timer value when in TPL, or perhaps for implementing a delay |
| 27 | function. This enables the drivers in drivers/timer as part of an |
| 28 | TPL build. |
| 29 | |
Simon Glass | 32f6c17 | 2016-02-24 09:14:49 -0700 | [diff] [blame] | 30 | config TIMER_EARLY |
| 31 | bool "Allow timer to be used early in U-Boot" |
| 32 | depends on TIMER |
Simon Glass | 6abd89b | 2018-09-02 17:02:24 -0600 | [diff] [blame] | 33 | # initr_bootstage() requires a timer and is called before initr_dm() |
| 34 | # so only the early timer is available |
| 35 | default y if X86 && BOOTSTAGE |
Simon Glass | 32f6c17 | 2016-02-24 09:14:49 -0700 | [diff] [blame] | 36 | help |
| 37 | In some cases the timer must be accessible before driver model is |
| 38 | active. Examples include when using CONFIG_TRACE to trace U-Boot's |
| 39 | execution before driver model is set up. Enable this option to |
| 40 | use an early timer. These functions must be supported by your timer |
| 41 | driver: timer_early_get_count() and timer_early_get_rate(). |
| 42 | |
Bin Meng | 19f88b2 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 43 | config AG101P_TIMER |
| 44 | bool "AG101P timer support" |
| 45 | depends on TIMER && NDS32 |
| 46 | help |
| 47 | Select this to enable a timer for AG01P devices. |
| 48 | |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 49 | config ALTERA_TIMER |
Bin Meng | 8a7b864 | 2015-11-13 00:11:14 -0800 | [diff] [blame] | 50 | bool "Altera timer support" |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 51 | depends on TIMER |
| 52 | help |
Bin Meng | 8a7b864 | 2015-11-13 00:11:14 -0800 | [diff] [blame] | 53 | Select this to enable a timer for Altera devices. Please find |
Thomas Chou | 221d2ac | 2015-10-22 22:28:53 +0800 | [diff] [blame] | 54 | details on the "Embedded Peripherals IP User Guide" of Altera. |
| 55 | |
Bin Meng | 19f88b2 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 56 | config ARC_TIMER |
| 57 | bool "ARC timer support" |
| 58 | depends on TIMER && ARC && CLK |
| 59 | help |
| 60 | Select this to enable built-in ARC timers. |
| 61 | ARC cores may have up to 2 built-in timers: timer0 and timer1, |
| 62 | usually at least one of them exists. Either of them is supported |
| 63 | in U-Boot. |
| 64 | |
| 65 | config AST_TIMER |
| 66 | bool "Aspeed ast2400/ast2500 timer support" |
| 67 | depends on TIMER |
| 68 | default y if ARCH_ASPEED |
| 69 | help |
| 70 | Select this to enable timer for Aspeed ast2400/ast2500 devices. |
| 71 | This is a simple sys timer driver, it is compatible with lib/time.c, |
| 72 | but does not support any interrupts. Even though SoC has 8 hardware |
| 73 | counters, they are all treated as a single device by this driver. |
| 74 | This is mostly because they all share several registers which |
| 75 | makes it difficult to completely separate them. |
| 76 | |
| 77 | config ATCPIT100_TIMER |
| 78 | bool "ATCPIT100 timer support" |
| 79 | depends on TIMER |
| 80 | help |
| 81 | Select this to enable a ATCPIT100 timer which will be embedded |
| 82 | in AE3XX, AE250 boards. |
| 83 | |
Wenyou.Yang@microchip.com | ce8a36f | 2017-08-15 17:40:26 +0800 | [diff] [blame] | 84 | config ATMEL_PIT_TIMER |
| 85 | bool "Atmel periodic interval timer support" |
| 86 | depends on TIMER |
| 87 | help |
| 88 | Select this to enable a periodic interval timer for Atmel devices, |
| 89 | it is designed to offer maximum accuracy and efficient management, |
| 90 | even for systems with long response time. |
| 91 | |
Michal Simek | c3caac5 | 2018-04-17 13:40:46 +0200 | [diff] [blame] | 92 | config CADENCE_TTC_TIMER |
| 93 | bool "Cadence TTC (Triple Timer Counter)" |
| 94 | depends on TIMER |
| 95 | help |
| 96 | Enables support for the cadence ttc driver. This driver is present |
| 97 | on Xilinx Zynq and ZynqMP SoCs. |
| 98 | |
Marek Vasut | 442c0f1 | 2018-08-18 15:58:32 +0200 | [diff] [blame] | 99 | config DESIGNWARE_APB_TIMER |
| 100 | bool "Designware APB Timer" |
| 101 | depends on TIMER |
| 102 | help |
| 103 | Enables support for the Designware APB Timer driver. This timer is |
| 104 | present on Altera SoCFPGA SoCs. |
| 105 | |
Bin Meng | 19f88b2 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 106 | config MPC83XX_TIMER |
| 107 | bool "MPC83xx timer support" |
| 108 | depends on TIMER |
Bin Meng | b2aa4c5 | 2015-11-13 00:11:24 -0800 | [diff] [blame] | 109 | help |
Bin Meng | 19f88b2 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 110 | Select this to enable support for the timer found on |
| 111 | devices based on the MPC83xx family of SoCs. |
Bin Meng | b2aa4c5 | 2015-11-13 00:11:24 -0800 | [diff] [blame] | 112 | |
Marek Vasut | 6be61c6 | 2019-05-04 17:30:58 +0200 | [diff] [blame] | 113 | config RENESAS_OSTM_TIMER |
| 114 | bool "Renesas RZ/A1 R7S72100 OSTM Timer" |
| 115 | depends on TIMER |
| 116 | help |
| 117 | Enables support for the Renesas OSTM Timer driver. |
| 118 | This timer is present on Renesas RZ/A1 R7S72100 SoCs. |
| 119 | |
Bin Meng | 855e657 | 2018-10-13 20:52:10 -0700 | [diff] [blame] | 120 | config X86_TSC_TIMER_EARLY_FREQ |
| 121 | int "x86 TSC timer frequency in MHz when used as the early timer" |
| 122 | depends on X86_TSC_TIMER |
| 123 | default 1000 |
| 124 | help |
| 125 | Sets the estimated CPU frequency in MHz when TSC is used as the |
| 126 | early timer and the frequency can neither be calibrated via some |
| 127 | hardware ways, nor got from device tree at the time when device |
| 128 | tree is not available yet. |
| 129 | |
Stephan Gerhold | 7b0c1c5 | 2020-01-04 18:45:15 +0100 | [diff] [blame] | 130 | config NOMADIK_MTU_TIMER |
| 131 | bool "Nomadik MTU Timer" |
| 132 | depends on TIMER |
| 133 | help |
| 134 | Enables support for the Nomadik Multi Timer Unit (MTU), |
| 135 | used in ST-Ericsson Ux500 SoCs. |
| 136 | The MTU provides 4 decrementing free-running timers. |
| 137 | At the moment, only the first timer is used by the driver. |
| 138 | |
Mugunthan V N | afae370 | 2015-12-24 16:08:07 +0530 | [diff] [blame] | 139 | config OMAP_TIMER |
| 140 | bool "Omap timer support" |
| 141 | depends on TIMER |
| 142 | help |
| 143 | Select this to enable an timer for Omap devices. |
| 144 | |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 145 | config RISCV_TIMER |
| 146 | bool "RISC-V timer support" |
| 147 | depends on TIMER && RISCV |
| 148 | help |
Sean Anderson | 9baaaef | 2020-09-28 10:52:21 -0400 | [diff] [blame] | 149 | Select this to enable support for a generic RISC-V S-Mode timer |
| 150 | driver. |
Bin Meng | 2539903 | 2018-12-12 06:12:27 -0800 | [diff] [blame] | 151 | |
Bin Meng | 19f88b2 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 152 | config ROCKCHIP_TIMER |
| 153 | bool "Rockchip timer support" |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 154 | depends on TIMER |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 155 | help |
Bin Meng | 19f88b2 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 156 | Select this to enable support for the timer found on |
| 157 | Rockchip devices. |
| 158 | |
| 159 | config SANDBOX_TIMER |
| 160 | bool "Sandbox timer support" |
| 161 | depends on SANDBOX && TIMER |
| 162 | help |
| 163 | Select this to enable an emulated timer for sandbox. It gets |
| 164 | time from host os. |
maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 165 | |
Patrice Chotard | 200a799 | 2017-02-21 13:37:05 +0100 | [diff] [blame] | 166 | config STI_TIMER |
| 167 | bool "STi timer support" |
| 168 | depends on TIMER |
| 169 | default y if ARCH_STI |
| 170 | help |
| 171 | Select this to enable a timer for STi devices. |
| 172 | |
Patrice Chotard | fdfefdc | 2018-02-07 10:44:45 +0100 | [diff] [blame] | 173 | config STM32_TIMER |
Bin Meng | 19f88b2 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 174 | bool "STM32 timer support" |
Patrice Chotard | fdfefdc | 2018-02-07 10:44:45 +0100 | [diff] [blame] | 175 | depends on TIMER |
| 176 | help |
| 177 | Select this to enable support for the timer found on |
| 178 | STM32 devices. |
| 179 | |
Bin Meng | 19f88b2 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 180 | config X86_TSC_TIMER |
| 181 | bool "x86 Time-Stamp Counter (TSC) timer support" |
| 182 | depends on TIMER && X86 |
Mario Six | 3c51655 | 2018-08-06 10:23:38 +0200 | [diff] [blame] | 183 | help |
Bin Meng | 19f88b2 | 2018-10-10 22:07:02 -0700 | [diff] [blame] | 184 | Select this to enable Time-Stamp Counter (TSC) timer for x86. |
Mario Six | 3c51655 | 2018-08-06 10:23:38 +0200 | [diff] [blame] | 185 | |
Simon Glass | d3edd42 | 2019-12-06 21:41:49 -0700 | [diff] [blame] | 186 | config X86_TSC_READ_BASE |
| 187 | bool "Read the TSC timer base on start-up" |
| 188 | depends on X86_TSC_TIMER |
| 189 | help |
| 190 | On x86 platforms the TSC timer tick starts at the value 0 on reset. |
| 191 | This it makes no sense to read the timer on boot and use that as the |
| 192 | base, since we will miss some time taken to load U-Boot, etc. This |
| 193 | delay is controlled by the SoC and we cannot reduce it, but for |
| 194 | bootstage we want to record the time since reset as accurately as |
| 195 | possible. |
| 196 | |
| 197 | The only exception is when U-Boot is used as a secondary bootloader, |
| 198 | where this option should be enabled. |
| 199 | |
Simon Glass | bba203e | 2019-12-06 21:41:50 -0700 | [diff] [blame] | 200 | config TPL_X86_TSC_TIMER_NATIVE |
| 201 | bool "x86 TSC timer uses native calibration" |
| 202 | depends on TPL && X86_TSC_TIMER |
| 203 | help |
| 204 | Selects native timer calibration for TPL and don't include the other |
| 205 | methods in the code. This helps to reduce code size in TPL and works |
| 206 | on fairly modern Intel chips. Code-size reductions is about 700 |
| 207 | bytes. |
| 208 | |
developer | 4a34735 | 2018-11-15 10:07:56 +0800 | [diff] [blame] | 209 | config MTK_TIMER |
| 210 | bool "MediaTek timer support" |
| 211 | depends on TIMER |
| 212 | help |
| 213 | Select this to enable support for the timer found on |
| 214 | MediaTek devices. |
| 215 | |
Thomas Chou | fb798b1 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 216 | endmenu |