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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Rick Chen36cb27c2017-12-26 13:55:53 +08002/*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
Rick Chen36cb27c2017-12-26 13:55:53 +08005 */
6
Rick Chen36cb27c2017-12-26 13:55:53 +08007#include <common.h>
Simon Glass8e201882020-05-10 11:39:54 -06008#include <flash.h>
Simon Glass2dc9c342020-05-10 11:40:01 -06009#include <image.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070010#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060011#include <net.h>
Rick Chen36cb27c2017-12-26 13:55:53 +080012#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
13#include <netdev.h>
14#endif
15#include <linux/io.h>
Rick Chencea16d02018-05-29 11:07:53 +080016#include <faraday/ftsmc020.h>
17#include <fdtdec.h>
Rick Chen9e017162019-08-28 18:46:07 +080018#include <dm.h>
Rick Chenc3027d02019-11-14 13:52:22 +080019#include <spl.h>
Rick Chen36cb27c2017-12-26 13:55:53 +080020
21DECLARE_GLOBAL_DATA_PTR;
22
Rick Chen2a218152018-12-03 17:48:20 +080023extern phys_addr_t prior_stage_fdt_address;
Rick Chen36cb27c2017-12-26 13:55:53 +080024/*
25 * Miscellaneous platform dependent initializations
26 */
27
28int board_init(void)
29{
Rick Chen36cb27c2017-12-26 13:55:53 +080030 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
31
32 return 0;
33}
34
35int dram_init(void)
36{
Rick Chen92038262019-11-14 13:52:23 +080037 return fdtdec_setup_mem_size_base();
Rick Chen36cb27c2017-12-26 13:55:53 +080038}
39
40int dram_init_banksize(void)
41{
Rick Chen92038262019-11-14 13:52:23 +080042 return fdtdec_setup_memory_banksize();
Rick Chen36cb27c2017-12-26 13:55:53 +080043}
44
45#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090046int board_eth_init(struct bd_info *bd)
Rick Chen36cb27c2017-12-26 13:55:53 +080047{
48 return ftmac100_initialize(bd);
49}
50#endif
51
52ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
53{
54 return 0;
55}
Rick Chen40a6fe72018-03-29 10:08:33 +080056
57void *board_fdt_blob_setup(void)
58{
Rick Chen40a6fe72018-03-29 10:08:33 +080059 return (void *)CONFIG_SYS_FDT_BASE;
60}
Rick Chencea16d02018-05-29 11:07:53 +080061
62int smc_init(void)
63{
64 int node = -1;
65 const char *compat = "andestech,atfsmc020";
66 void *blob = (void *)gd->fdt_blob;
67 fdt_addr_t addr;
68 struct ftsmc020_bank *regs;
69
70 node = fdt_node_offset_by_compatible(blob, -1, compat);
71 if (node < 0)
72 return -FDT_ERR_NOTFOUND;
73
Rick Chenca3e5e42020-07-17 16:24:44 +080074 addr = fdtdec_get_addr_size_auto_noparent(blob, node,
75 "reg", 0, NULL, false);
Rick Chencea16d02018-05-29 11:07:53 +080076
77 if (addr == FDT_ADDR_T_NONE)
78 return -EINVAL;
79
80 regs = (struct ftsmc020_bank *)addr;
81 regs->cr &= ~FTSMC020_BANK_WPROT;
82
83 return 0;
84}
85
Rick Chen9e017162019-08-28 18:46:07 +080086static void v5l2_init(void)
87{
88 struct udevice *dev;
89
90 uclass_get_device(UCLASS_CACHE, 0, &dev);
91}
92
Rick Chencea16d02018-05-29 11:07:53 +080093#ifdef CONFIG_BOARD_EARLY_INIT_F
94int board_early_init_f(void)
95{
96 smc_init();
Rick Chen9e017162019-08-28 18:46:07 +080097 v5l2_init();
Rick Chencea16d02018-05-29 11:07:53 +080098
99 return 0;
100}
101#endif
Rick Chenc3027d02019-11-14 13:52:22 +0800102
103#ifdef CONFIG_SPL
104void board_boot_order(u32 *spl_boot_list)
105{
106 u8 i;
107 u32 boot_devices[] = {
108#ifdef CONFIG_SPL_RAM_SUPPORT
109 BOOT_DEVICE_RAM,
110#endif
111#ifdef CONFIG_SPL_MMC_SUPPORT
112 BOOT_DEVICE_MMC1,
113#endif
114 };
115
116 for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
117 spl_boot_list[i] = boot_devices[i];
118}
119#endif
120
121#ifdef CONFIG_SPL_LOAD_FIT
122int board_fit_config_name_match(const char *name)
123{
124 /* boot using first FIT config */
125 return 0;
126}
127#endif