blob: d08316870553fd44a63e68d2573c95090deb6396 [file] [log] [blame]
Alexey Brodkinc15be5b2018-01-24 21:37:14 +03001/*
2 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <config.h>
8
9MEMORY {
10 ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
11 RAM : ORIGIN = RAM_DATA_BASE, LENGTH = RAM_DATA_SIZE
12}
13
14OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
15OUTPUT_ARCH(arc)
16ENTRY(_start)
17SECTIONS
18{
19 . = CONFIG_SYS_MONITOR_BASE;
20 __image_copy_start = .;
21 .ivt :
22 {
23 __ivt_start = .;
24 KEEP(*(.ivt));
25 __ivt_end = .;
26 } > ROM
27
28 . = ALIGN(1024);
29 .text : {
30 __text_start = .;
31 arch/arc/lib/start.o (.text*)
32 *(.text*)
33 __text_end = .;
34 } > ROM
35
36 . = ALIGN(4);
37 .rodata : {
38 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
39 } > ROM
40
41 . = ALIGN(4);
42 .u_boot_list : {
43 KEEP(*(SORT(.u_boot_list*)));
44
45 /* Mark RAM's LMA */
46 . = ALIGN(4);
47 __rom_end = .;
48 } > ROM
49
50 .data : {
51 /* Mark RAM's VMA */
52 . = ALIGN(4);
53
54 /*
55 * Everything between __ram_start and __ram_start will be
56 * copied from ROM to RAM in board_early_init_f().
57 */
58 __ram_start = .;
59
60 *(.data*)
61
62 __ram_end = .;
63 } > RAM AT > ROM
64
65 .bss : {
66 . = ALIGN(1024);
67 __bss_start = .;
68 *(.bss*)
69 __bss_end = .;
70 } > RAM
71
72 /* Keep relocation-related symbols to make linker happy */
73 __rel_dyn_start = .;
74 __rel_dyn_end = .;
75 __image_copy_end = .;
76 __init_end = .;
77}