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git01.mediatek.com / filogic / uboot / ddf6e6aeebb06215e9cdc7abc86bad0202144ca0 / . / board / Marvell / sheevaplug / sheevaplug.c
blob: 6311ed3b2e5933eadc712f4c5800299afa707d35 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]2/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]6 */
7
8#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]9#include <init.h>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]10#include <miiphy.h>
Simon Glass0c364412019-12-28 10:44:48 -0700[diff] [blame]11#include <net.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -0600[diff] [blame]12#include <asm/mach-types.h>
Lei Wen298ae912011-10-18 20:11:42 +0530[diff] [blame]13#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]14#include <asm/arch/soc.h>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]15#include <asm/arch/mpp.h>
16#include "sheevaplug.h"
17
18DECLARE_GLOBAL_DATA_PTR;
19
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]20int board_early_init_f(void)
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]21{
22 /*
23 * default gpio configuration
24 * There are maximum 64 gpios controlled through 2 sets of registers
25 * the below configuration configures mainly initial LED status
26 */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]27 mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
28 SHEEVAPLUG_OE_VAL_HIGH,
29 SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]30
31 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]32 static const u32 kwmpp_config[] = {
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]33 MPP0_NF_IO2,
34 MPP1_NF_IO3,
35 MPP2_NF_IO4,
36 MPP3_NF_IO5,
37 MPP4_NF_IO6,
38 MPP5_NF_IO7,
39 MPP6_SYSRST_OUTn,
40 MPP7_GPO,
41 MPP8_UART0_RTS,
42 MPP9_UART0_CTS,
43 MPP10_UART0_TXD,
44 MPP11_UART0_RXD,
45 MPP12_SD_CLK,
46 MPP13_SD_CMD,
47 MPP14_SD_D0,
48 MPP15_SD_D1,
49 MPP16_SD_D2,
50 MPP17_SD_D3,
51 MPP18_NF_IO0,
52 MPP19_NF_IO1,
53 MPP20_GPIO,
54 MPP21_GPIO,
55 MPP22_GPIO,
56 MPP23_GPIO,
57 MPP24_GPIO,
58 MPP25_GPIO,
59 MPP26_GPIO,
60 MPP27_GPIO,
61 MPP28_GPIO,
62 MPP29_TSMP9,
63 MPP30_GPIO,
64 MPP31_GPIO,
65 MPP32_GPIO,
66 MPP33_GPIO,
67 MPP34_GPIO,
68 MPP35_GPIO,
69 MPP36_GPIO,
70 MPP37_GPIO,
71 MPP38_GPIO,
72 MPP39_GPIO,
73 MPP40_GPIO,
74 MPP41_GPIO,
75 MPP42_GPIO,
76 MPP43_GPIO,
77 MPP44_GPIO,
78 MPP45_GPIO,
79 MPP46_GPIO,
80 MPP47_GPIO,
81 MPP48_GPIO,
82 MPP49_GPIO,
83 0
84 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]85 kirkwood_mpp_conf(kwmpp_config, NULL);
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]86 return 0;
87}
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]88
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]89int board_init(void)
90{
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]91 /*
92 * arch number of board
93 */
94 gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
95
96 /* adress of boot parameters */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]97 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]98
99 return 0;
100}
101
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]102#ifdef CONFIG_RESET_PHY_R
103/* Configure and enable MV88E1116 PHY */
104void reset_phy(void)
105{
106 u16 reg;
107 u16 devadr;
108 char *name = "egiga0";
109
110 if (miiphy_set_current_dev(name))
111 return;
112
113 /* command to read PHY dev address */
114 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
115 printf("Err..%s could not read PHY dev address\n",
116 __FUNCTION__);
117 return;
118 }
119
120 /*
121 * Enable RGMII delay on Tx and Rx for CPU port
122 * Ref: sec 4.7.2 of chip datasheet
123 */
124 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
125 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
126 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
127 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
128 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
129
130 /* reset the phy */
131 miiphy_reset(name, devadr);
132
133 printf("88E1116 Initialized on %s\n", name);
134}
135#endif /* CONFIG_RESET_PHY_R */