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git01.mediatek.com / filogic / uboot / ddbcf95bd4b69762f3d8007658c48820665fbbee / . / board / adder / u-boot.lds
blob: 25aaa7d8ff34f301713be6818c41a7f32c7b12ff [file] [log] [blame]
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]1/*
2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Modified by Yuli Barcohen <yuli@arabellasw.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26OUTPUT_ARCH(powerpc)
27SECTIONS
28{
29 /* Read-only sections, merged into text segment: */
30 . = + SIZEOF_HEADERS;
31 .interp : { *(.interp) }
32 .hash : { *(.hash) }
33 .dynsym : { *(.dynsym) }
34 .dynstr : { *(.dynstr) }
35 .rel.text : { *(.rel.text) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]36 .rela.text : { *(.rela.text) }
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]37 .rel.data : { *(.rel.data) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]38 .rela.data : { *(.rela.data) }
39 .rel.rodata : { *(.rel.rodata) }
40 .rela.rodata : { *(.rela.rodata) }
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]41 .rel.got : { *(.rel.got) }
42 .rela.got : { *(.rela.got) }
43 .rel.ctors : { *(.rel.ctors) }
44 .rela.ctors : { *(.rela.ctors) }
45 .rel.dtors : { *(.rel.dtors) }
46 .rela.dtors : { *(.rela.dtors) }
47 .rel.bss : { *(.rel.bss) }
48 .rela.bss : { *(.rela.bss) }
49 .rel.plt : { *(.rel.plt) }
50 .rela.plt : { *(.rela.plt) }
51 .init : { *(.init) }
52 .plt : { *(.plt) }
53 .text :
54 {
55 cpu/mpc8xx/start.o (.text)
56 *(.text)
57 *(.fixup)
58 *(.got1)
59 . = ALIGN(16);
60 *(.rodata)
61 *(.rodata1)
62 *(.rodata.str1.4)
Wolfgang Denkaaa7c002005-12-12 16:06:05 +0100[diff] [blame]63 *(.eh_frame)
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]64 }
65 .fini : { *(.fini) } =0
66 .ctors : { *(.ctors) }
67 .dtors : { *(.dtors) }
68
69 /* Read-write section, merged into data segment: */
70 . = (. + 0x0FFF) & 0xFFFFF000;
71 _erotext = .;
72 PROVIDE (erotext = .);
73 .reloc :
74 {
75 *(.got)
76 _GOT2_TABLE_ = .;
77 *(.got2)
78 _FIXUP_TABLE_ = .;
79 *(.fixup)
80 }
81 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
82 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
83
84 .data :
85 {
86 *(.data)
87 *(.data1)
88 *(.sdata)
89 *(.sdata2)
90 *(.dynamic)
91 CONSTRUCTORS
92 }
93 _edata = .;
94 PROVIDE (edata = .);
95
Wolfgang Denk5dd2c652005-08-31 12:28:00 +0200[diff] [blame]96 . = .;
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]97 __u_boot_cmd_start = .;
98 .u_boot_cmd : { *(.u_boot_cmd) }
99 __u_boot_cmd_end = .;
100
101
Wolfgang Denk5dd2c652005-08-31 12:28:00 +0200[diff] [blame]102 . = .;
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]103 __start___ex_table = .;
104 __ex_table : { *(__ex_table) }
105 __stop___ex_table = .;
106
107 . = ALIGN(4096);
108 __init_begin = .;
109 .text.init : { *(.text.init) }
110 .data.init : { *(.data.init) }
111 . = ALIGN(4096);
112 __init_end = .;
113
114 __bss_start = .;
Wolfgang Denk828a9782008-01-12 20:31:39 +0100[diff] [blame]115 .bss (NOLOAD) :
wdenk9f664dd2004-06-09 21:50:45 +0000[diff] [blame]116 {
117 *(.sbss) *(.scommon)
118 *(.dynbss)
119 *(.bss)
120 *(COMMON)
121 }
122 _end = . ;
123 PROVIDE (end = .);
124}
125ENTRY(_start)