| wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * MCF5282 Internal Memory Map |
| 3 | * |
| 4 | * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #ifndef __IMMAP_5282__ |
| 26 | #define __IMMAP_5282__ |
| 27 | |
| 28 | |
| 29 | /* Fast ethernet controller registers |
| 30 | */ |
| 31 | typedef struct fec { |
| 32 | uint fec_ecntrl; /* ethernet control register */ |
| 33 | uint fec_ievent; /* interrupt event register */ |
| 34 | uint fec_imask; /* interrupt mask register */ |
| 35 | uint fec_ivec; /* interrupt level and vector status */ |
| 36 | uint fec_r_des_active; /* Rx ring updated flag */ |
| 37 | uint fec_x_des_active; /* Tx ring updated flag */ |
| 38 | uint res3[10]; /* reserved */ |
| 39 | uint fec_mii_data; /* MII data register */ |
| 40 | uint fec_mii_speed; /* MII speed control register */ |
| 41 | uint res4[17]; /* reserved */ |
| 42 | uint fec_r_bound; /* end of RAM (read-only) */ |
| 43 | uint fec_r_fstart; /* Rx FIFO start address */ |
| 44 | uint res5[6]; /* reserved */ |
| 45 | uint fec_x_fstart; /* Tx FIFO start address */ |
| 46 | uint res7[21]; /* reserved */ |
| 47 | uint fec_r_cntrl; /* Rx control register */ |
| 48 | uint fec_r_hash; /* Rx hash register */ |
| 49 | uint res8[14]; /* reserved */ |
| 50 | uint fec_x_cntrl; /* Tx control register */ |
| 51 | uint res9[0x9e]; /* reserved */ |
| 52 | uint fec_addr_low; /* lower 32 bits of station address */ |
| 53 | uint fec_addr_high; /* upper 16 bits of station address */ |
| 54 | uint fec_hash_table_high; /* upper 32-bits of hash table */ |
| 55 | uint fec_hash_table_low; /* lower 32-bits of hash table */ |
| 56 | uint fec_r_des_start; /* beginning of Rx descriptor ring */ |
| 57 | uint fec_x_des_start; /* beginning of Tx descriptor ring */ |
| 58 | uint fec_r_buff_size; /* Rx buffer size */ |
| 59 | uint res2[9]; /* reserved */ |
| 60 | uchar fec_fifo[960]; /* fifo RAM */ |
| 61 | } fec_t; |
| 62 | |
| 63 | #endif /* __IMMAP_5282__ */ |