blob: 623c6915b81f5ba1fef1dfa249503bd7880c5353 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
maxims@google.com2d5a2ad2017-01-18 13:44:56 -08002/*
3 * (C) Copyright 2016 Google, Inc
maxims@google.com2d5a2ad2017-01-18 13:44:56 -08004 */
5
6#include <common.h>
7#include <clk-uclass.h>
8#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060010#include <asm/global_data.h>
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080011#include <asm/io.h>
12#include <asm/arch/scu_ast2500.h>
13#include <dm/lists.h>
Ryan Chen5e6c9f02020-08-31 14:03:03 +080014#include <dt-bindings/clock/aspeed-clock.h>
Joel Stanleydd8c0842022-06-23 18:35:32 +093015#include <dt-bindings/reset/ast2500-reset.h>
Simon Glassdbd79542020-05-10 11:40:11 -060016#include <linux/delay.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070017#include <linux/err.h>
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080018
maxims@google.com15016af2017-04-17 12:00:32 -070019/*
20 * MAC Clock Delay settings, taken from Aspeed SDK
21 */
22#define RGMII_TXCLK_ODLY 8
23#define RMII_RXCLK_IDLY 2
24
25/*
26 * TGMII Clock Duty constants, taken from Aspeed SDK
27 */
28#define RGMII2_TXCK_DUTY 0x66
29#define RGMII1_TXCK_DUTY 0x64
30
31#define D2PLL_DEFAULT_RATE (250 * 1000 * 1000)
32
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080033DECLARE_GLOBAL_DATA_PTR;
34
35/*
maxims@google.com15016af2017-04-17 12:00:32 -070036 * Clock divider/multiplier configuration struct.
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080037 * For H-PLL and M-PLL the formula is
38 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
39 * M - Numerator
40 * N - Denumerator
41 * P - Post Divider
42 * They have the same layout in their control register.
maxims@google.com15016af2017-04-17 12:00:32 -070043 *
44 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
45 * yet needed and ignored by clock configurations.
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080046 */
maxims@google.com15016af2017-04-17 12:00:32 -070047struct ast2500_div_config {
48 unsigned int num;
49 unsigned int denum;
50 unsigned int post_div;
51};
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080052
53/*
54 * Get the rate of the M-PLL clock from input clock frequency and
55 * the value of the M-PLL Parameter Register.
56 */
57static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
58{
maxims@google.coma91f1d22017-04-17 12:00:33 -070059 const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
60 const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
61 >> SCU_MPLL_DENUM_SHIFT;
62 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
63 >> SCU_MPLL_POST_SHIFT;
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080064
maxims@google.comd0672172017-01-30 11:35:04 -080065 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080066}
67
68/*
69 * Get the rate of the H-PLL clock from input clock frequency and
70 * the value of the H-PLL Parameter Register.
71 */
72static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
73{
maxims@google.coma91f1d22017-04-17 12:00:33 -070074 const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
75 const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
76 >> SCU_HPLL_DENUM_SHIFT;
77 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
78 >> SCU_HPLL_POST_SHIFT;
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080079
maxims@google.comd0672172017-01-30 11:35:04 -080080 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080081}
82
83static ulong ast2500_get_clkin(struct ast2500_scu *scu)
84{
85 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ
86 ? 25 * 1000 * 1000 : 24 * 1000 * 1000;
87}
88
89/**
90 * Get current rate or uart clock
91 *
92 * @scu SCU registers
93 * @uart_index UART index, 1-5
94 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010095 * Return: current setting for uart clock rate
maxims@google.com2d5a2ad2017-01-18 13:44:56 -080096 */
97static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index)
98{
99 /*
100 * ast2500 datasheet is very confusing when it comes to UART clocks,
101 * especially when CLKIN = 25 MHz. The settings are in
102 * different registers and it is unclear how they interact.
103 *
104 * This has only been tested with default settings and CLKIN = 24 MHz.
105 */
106 ulong uart_clkin;
107
108 if (readl(&scu->misc_ctrl2) &
109 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT)))
110 uart_clkin = 192 * 1000 * 1000;
111 else
112 uart_clkin = 24 * 1000 * 1000;
113
114 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13)
115 uart_clkin /= 13;
116
117 return uart_clkin;
118}
119
120static ulong ast2500_clk_get_rate(struct clk *clk)
121{
122 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
123 ulong clkin = ast2500_get_clkin(priv->scu);
124 ulong rate;
125
126 switch (clk->id) {
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800127 case ASPEED_CLK_HPLL:
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800128 /*
129 * This ignores dynamic/static slowdown of ARMCLK and may
130 * be inaccurate.
131 */
132 rate = ast2500_get_hpll_rate(clkin,
133 readl(&priv->scu->h_pll_param));
134 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800135 case ASPEED_CLK_MPLL:
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800136 rate = ast2500_get_mpll_rate(clkin,
137 readl(&priv->scu->m_pll_param));
138 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800139 case ASPEED_CLK_APB:
maxims@google.com995167b2017-04-17 12:00:29 -0700140 {
141 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
maxims@google.coma91f1d22017-04-17 12:00:33 -0700142 & SCU_PCLK_DIV_MASK)
143 >> SCU_PCLK_DIV_SHIFT);
maxims@google.com995167b2017-04-17 12:00:29 -0700144 rate = ast2500_get_hpll_rate(clkin,
maxims@google.coma91f1d22017-04-17 12:00:33 -0700145 readl(&priv->
146 scu->h_pll_param));
maxims@google.com995167b2017-04-17 12:00:29 -0700147 rate = rate / apb_div;
148 }
149 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800150 case ASPEED_CLK_SDIO:
Eddie Jamesb7d76ac2019-08-15 14:29:37 -0500151 {
152 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
153 & SCU_SDCLK_DIV_MASK)
154 >> SCU_SDCLK_DIV_SHIFT);
155 rate = ast2500_get_hpll_rate(clkin,
156 readl(&priv->
157 scu->h_pll_param));
158 rate = rate / apb_div;
159 }
160 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800161 case ASPEED_CLK_GATE_UART1CLK:
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800162 rate = ast2500_get_uart_clk_rate(priv->scu, 1);
163 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800164 case ASPEED_CLK_GATE_UART2CLK:
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800165 rate = ast2500_get_uart_clk_rate(priv->scu, 2);
166 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800167 case ASPEED_CLK_GATE_UART3CLK:
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800168 rate = ast2500_get_uart_clk_rate(priv->scu, 3);
169 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800170 case ASPEED_CLK_GATE_UART4CLK:
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800171 rate = ast2500_get_uart_clk_rate(priv->scu, 4);
172 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800173 case ASPEED_CLK_GATE_UART5CLK:
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800174 rate = ast2500_get_uart_clk_rate(priv->scu, 5);
175 break;
176 default:
Joel Stanley50ddb952022-06-23 18:35:30 +0930177 debug("%s: unknown clk %ld\n", __func__, clk->id);
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800178 return -ENOENT;
179 }
180
181 return rate;
182}
183
Cédric Le Goaterd7f37892018-10-29 07:06:41 +0100184struct ast2500_clock_config {
185 ulong input_rate;
186 ulong rate;
187 struct ast2500_div_config cfg;
188};
189
190static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
191 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
192};
193
194static bool ast2500_get_clock_config_default(ulong input_rate,
195 ulong requested_rate,
196 struct ast2500_div_config *cfg)
197{
198 int i;
199
200 for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
201 const struct ast2500_clock_config *default_cfg =
202 &ast2500_clock_config_defaults[i];
203 if (default_cfg->input_rate == input_rate &&
204 default_cfg->rate == requested_rate) {
205 *cfg = default_cfg->cfg;
206 return true;
207 }
208 }
209
210 return false;
211}
212
maxims@google.com15016af2017-04-17 12:00:32 -0700213/*
214 * @input_rate - the rate of input clock in Hz
215 * @requested_rate - desired output rate in Hz
216 * @div - this is an IN/OUT parameter, at input all fields of the config
217 * need to be set to their maximum allowed values.
218 * The result (the best config we could find), would also be returned
219 * in this structure.
220 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100221 * Return: The clock rate, when the resulting div_config is used.
maxims@google.com15016af2017-04-17 12:00:32 -0700222 */
223static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate,
224 struct ast2500_div_config *cfg)
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800225{
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800226 /*
maxims@google.com15016af2017-04-17 12:00:32 -0700227 * The assumption is that kHz precision is good enough and
228 * also enough to avoid overflow when multiplying.
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800229 */
maxims@google.com15016af2017-04-17 12:00:32 -0700230 const ulong input_rate_khz = input_rate / 1000;
231 const ulong rate_khz = requested_rate / 1000;
232 const struct ast2500_div_config max_vals = *cfg;
233 struct ast2500_div_config it = { 0, 0, 0 };
234 ulong delta = rate_khz;
235 ulong new_rate_khz = 0;
236
Cédric Le Goaterd7f37892018-10-29 07:06:41 +0100237 /*
238 * Look for a well known frequency first.
239 */
240 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
241 return requested_rate;
242
maxims@google.com15016af2017-04-17 12:00:32 -0700243 for (; it.denum <= max_vals.denum; ++it.denum) {
244 for (it.post_div = 0; it.post_div <= max_vals.post_div;
245 ++it.post_div) {
246 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz)
247 * (it.denum + 1);
248 if (it.num > max_vals.num)
249 continue;
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800250
maxims@google.com15016af2017-04-17 12:00:32 -0700251 new_rate_khz = (input_rate_khz
252 * ((it.num + 1) / (it.denum + 1)))
253 / (it.post_div + 1);
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800254
255 /* Keep the rate below requested one. */
256 if (new_rate_khz > rate_khz)
257 continue;
258
259 if (new_rate_khz - rate_khz < delta) {
260 delta = new_rate_khz - rate_khz;
maxims@google.com15016af2017-04-17 12:00:32 -0700261 *cfg = it;
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800262 if (delta == 0)
maxims@google.com15016af2017-04-17 12:00:32 -0700263 return new_rate_khz * 1000;
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800264 }
265 }
266 }
267
maxims@google.com15016af2017-04-17 12:00:32 -0700268 return new_rate_khz * 1000;
269}
270
271static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
272{
273 ulong clkin = ast2500_get_clkin(scu);
274 u32 mpll_reg;
275 struct ast2500_div_config div_cfg = {
maxims@google.coma91f1d22017-04-17 12:00:33 -0700276 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT),
277 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT),
278 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT),
maxims@google.com15016af2017-04-17 12:00:32 -0700279 };
280
281 ast2500_calc_clock_config(clkin, rate, &div_cfg);
282
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800283 mpll_reg = readl(&scu->m_pll_param);
maxims@google.coma91f1d22017-04-17 12:00:33 -0700284 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK
285 | SCU_MPLL_DENUM_MASK);
maxims@google.com15016af2017-04-17 12:00:32 -0700286 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT)
287 | (div_cfg.num << SCU_MPLL_NUM_SHIFT)
288 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT);
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800289
maxims@google.comadea66c2017-04-17 12:00:23 -0700290 ast_scu_unlock(scu);
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800291 writel(mpll_reg, &scu->m_pll_param);
maxims@google.comadea66c2017-04-17 12:00:23 -0700292 ast_scu_lock(scu);
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800293
294 return ast2500_get_mpll_rate(clkin, mpll_reg);
295}
296
maxims@google.com15016af2017-04-17 12:00:32 -0700297static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index)
298{
299 ulong clkin = ast2500_get_clkin(scu);
300 ulong hpll_rate = ast2500_get_hpll_rate(clkin,
301 readl(&scu->h_pll_param));
302 ulong required_rate;
303 u32 hwstrap;
304 u32 divisor;
305 u32 reset_bit;
306 u32 clkstop_bit;
307
308 /*
309 * According to data sheet, for 10/100 mode the MAC clock frequency
310 * should be at least 25MHz and for 1000 mode at least 100MHz
311 */
312 hwstrap = readl(&scu->hwstrap);
313 if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII))
314 required_rate = 100 * 1000 * 1000;
315 else
316 required_rate = 25 * 1000 * 1000;
317
318 divisor = hpll_rate / required_rate;
319
320 if (divisor < 4) {
321 /* Clock can't run fast enough, but let's try anyway */
322 debug("MAC clock too slow\n");
323 divisor = 4;
324 } else if (divisor > 16) {
325 /* Can't slow down the clock enough, but let's try anyway */
326 debug("MAC clock too fast\n");
327 divisor = 16;
328 }
329
330 switch (index) {
331 case 1:
332 reset_bit = SCU_SYSRESET_MAC1;
333 clkstop_bit = SCU_CLKSTOP_MAC1;
334 break;
335 case 2:
336 reset_bit = SCU_SYSRESET_MAC2;
337 clkstop_bit = SCU_CLKSTOP_MAC2;
338 break;
339 default:
340 return -EINVAL;
341 }
342
343 ast_scu_unlock(scu);
344 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK,
345 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT);
346
347 /*
348 * Disable MAC, start its clock and re-enable it.
349 * The procedure and the delays (100us & 10ms) are
350 * specified in the datasheet.
351 */
352 setbits_le32(&scu->sysreset_ctrl1, reset_bit);
353 udelay(100);
354 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
355 mdelay(10);
356 clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
357
358 writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
359 | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT),
360 &scu->clk_duty_sel);
361
362 ast_scu_lock(scu);
363
364 return required_rate;
365}
366
367static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
368{
369 /*
370 * The values and the meaning of the next three
371 * parameters are undocumented. Taken from Aspeed SDK.
Cédric Le Goaterd7f37892018-10-29 07:06:41 +0100372 *
373 * TODO(clg@kaod.org): the SIP and SIC values depend on the
374 * Numerator value
maxims@google.com15016af2017-04-17 12:00:32 -0700375 */
376 const u32 d2_pll_ext_param = 0x2c;
377 const u32 d2_pll_sip = 0x11;
378 const u32 d2_pll_sic = 0x18;
379 u32 clk_delay_settings =
380 (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
381 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
382 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
383 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT);
384 struct ast2500_div_config div_cfg = {
385 .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT,
386 .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT,
387 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT,
388 };
389 ulong clkin = ast2500_get_clkin(scu);
390 ulong new_rate;
391
392 ast_scu_unlock(scu);
393 writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT)
394 | SCU_D2PLL_EXT1_OFF
395 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]);
396
397 /*
398 * Select USB2.0 port1 PHY clock as a clock source for GCRT.
399 * This would disconnect it from D2-PLL.
400 */
401 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF,
402 SCU_MISC_GCRT_USB20CLK);
403
404 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg);
405 writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT)
406 | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT)
407 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT)
408 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT)
409 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT),
410 &scu->d2_pll_param);
411
412 clrbits_le32(&scu->d2_pll_ext_param[0],
413 SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET);
414
415 clrsetbits_le32(&scu->misc_ctrl2,
416 SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL
417 | SCU_MISC2_RGMII_CLKDIV_MASK |
418 SCU_MISC2_RMII_CLKDIV_MASK,
419 (4 << SCU_MISC2_RMII_CLKDIV_SHIFT));
420
421 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay);
422 writel(clk_delay_settings, &scu->mac_clk_delay_100M);
423 writel(clk_delay_settings, &scu->mac_clk_delay_10M);
424
425 ast_scu_lock(scu);
426
427 return new_rate;
428}
429
Joel Stanleydd8c0842022-06-23 18:35:32 +0930430#define SCU_CLKSTOP_SDIO 27
431static ulong ast2500_enable_sdclk(struct ast2500_scu *scu)
432{
433 u32 reset_bit;
434 u32 clkstop_bit;
435
436 reset_bit = BIT(ASPEED_RESET_SDIO);
437 clkstop_bit = BIT(SCU_CLKSTOP_SDIO);
438
439 setbits_le32(&scu->sysreset_ctrl1, reset_bit);
440 udelay(100);
441 //enable clk
442 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
443 mdelay(10);
444 clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
445
446 return 0;
447}
448
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800449static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
450{
451 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
452
453 ulong new_rate;
454 switch (clk->id) {
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800455 case ASPEED_CLK_MPLL:
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800456 new_rate = ast2500_configure_ddr(priv->scu, rate);
457 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800458 case ASPEED_CLK_D2PLL:
maxims@google.com15016af2017-04-17 12:00:32 -0700459 new_rate = ast2500_configure_d2pll(priv->scu, rate);
460 break;
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800461 default:
Joel Stanley50ddb952022-06-23 18:35:30 +0930462 debug("%s: unknown clk %ld\n", __func__, clk->id);
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800463 return -ENOENT;
464 }
465
466 return new_rate;
467}
468
maxims@google.com15016af2017-04-17 12:00:32 -0700469static int ast2500_clk_enable(struct clk *clk)
470{
471 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
472
473 switch (clk->id) {
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800474 case ASPEED_CLK_SDIO:
Eddie Jamesb7d76ac2019-08-15 14:29:37 -0500475 if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
476 ast_scu_unlock(priv->scu);
477
478 setbits_le32(&priv->scu->sysreset_ctrl1,
479 SCU_SYSRESET_SDIO);
480 udelay(100);
481 clrbits_le32(&priv->scu->clk_stop_ctrl1,
482 SCU_CLKSTOP_SDCLK);
483 mdelay(10);
484 clrbits_le32(&priv->scu->sysreset_ctrl1,
485 SCU_SYSRESET_SDIO);
486
487 ast_scu_lock(priv->scu);
488 }
489 break;
maxims@google.com15016af2017-04-17 12:00:32 -0700490 /*
491 * For MAC clocks the clock rate is
492 * configured based on whether RGMII or RMII mode has been selected
493 * through hardware strapping.
494 */
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800495 case ASPEED_CLK_GATE_MAC1CLK:
maxims@google.com15016af2017-04-17 12:00:32 -0700496 ast2500_configure_mac(priv->scu, 1);
497 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800498 case ASPEED_CLK_GATE_MAC2CLK:
maxims@google.com15016af2017-04-17 12:00:32 -0700499 ast2500_configure_mac(priv->scu, 2);
500 break;
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800501 case ASPEED_CLK_D2PLL:
maxims@google.com15016af2017-04-17 12:00:32 -0700502 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
Cédric Le Goater62b4bfd2018-10-29 07:06:37 +0100503 break;
Joel Stanleydd8c0842022-06-23 18:35:32 +0930504 case ASPEED_CLK_GATE_SDCLK:
505 ast2500_enable_sdclk(priv->scu);
506 break;
maxims@google.com15016af2017-04-17 12:00:32 -0700507 default:
Joel Stanley50ddb952022-06-23 18:35:30 +0930508 debug("%s: unknown clk %ld\n", __func__, clk->id);
maxims@google.com15016af2017-04-17 12:00:32 -0700509 return -ENOENT;
510 }
511
512 return 0;
513}
514
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800515struct clk_ops ast2500_clk_ops = {
516 .get_rate = ast2500_clk_get_rate,
517 .set_rate = ast2500_clk_set_rate,
maxims@google.com15016af2017-04-17 12:00:32 -0700518 .enable = ast2500_clk_enable,
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800519};
520
Simon Glassaad29ae2020-12-03 16:55:21 -0700521static int ast2500_clk_of_to_plat(struct udevice *dev)
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800522{
523 struct ast2500_clk_priv *priv = dev_get_priv(dev);
524
Ryan Chen1e4a5c12020-08-31 14:03:04 +0800525 priv->scu = devfdt_get_addr_ptr(dev);
526 if (IS_ERR(priv->scu))
527 return PTR_ERR(priv->scu);
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800528
529 return 0;
530}
531
532static int ast2500_clk_bind(struct udevice *dev)
533{
534 int ret;
535
536 /* The reset driver does not have a device node, so bind it here */
537 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
538 if (ret)
539 debug("Warning: No reset driver: ret=%d\n", ret);
540
541 return 0;
542}
543
544static const struct udevice_id ast2500_clk_ids[] = {
545 { .compatible = "aspeed,ast2500-scu" },
546 { }
547};
548
549U_BOOT_DRIVER(aspeed_ast2500_scu) = {
550 .name = "aspeed_ast2500_scu",
551 .id = UCLASS_CLK,
552 .of_match = ast2500_clk_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700553 .priv_auto = sizeof(struct ast2500_clk_priv),
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800554 .ops = &ast2500_clk_ops,
555 .bind = ast2500_clk_bind,
Simon Glassaad29ae2020-12-03 16:55:21 -0700556 .of_to_plat = ast2500_clk_of_to_plat,
maxims@google.com2d5a2ad2017-01-18 13:44:56 -0800557};