Matthias Fuchs | c6c882e | 2007-12-28 17:07:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com |
| 4 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com |
| 5 | * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com |
| 6 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
| 7 | * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com |
| 8 | * |
| 9 | * (C) Copyright 2006-2007 |
| 10 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | /* define DEBUG for debug output */ |
| 29 | #undef DEBUG |
| 30 | |
| 31 | #include <common.h> |
| 32 | #include <asm/processor.h> |
| 33 | #include <asm/io.h> |
| 34 | #include <ppc440.h> |
| 35 | |
Matthias Fuchs | 88f4a7b | 2008-01-02 16:48:34 +0100 | [diff] [blame] | 36 | extern int denali_wait_for_dlllock(void); |
| 37 | extern void denali_core_search_data_eye(void); |
Matthias Fuchs | c6c882e | 2007-12-28 17:07:14 +0100 | [diff] [blame] | 38 | |
Matthias Fuchs | c6c882e | 2007-12-28 17:07:14 +0100 | [diff] [blame] | 39 | |
| 40 | #if defined(CONFIG_NAND_SPL) |
| 41 | /* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big |
| 42 | * for the 4k NAND boot image so define bus_frequency to 133MHz here |
| 43 | * which is save for the refresh counter setup. |
| 44 | */ |
| 45 | #define get_bus_freq(val) 133000000 |
| 46 | #endif |
| 47 | |
| 48 | /************************************************************************* |
| 49 | * |
| 50 | * initdram -- 440EPx's DDR controller is a DENALI Core |
| 51 | * |
| 52 | ************************************************************************/ |
Becky Bruce | bd99ae7 | 2008-06-09 16:03:40 -0500 | [diff] [blame] | 53 | phys_size_t initdram (int board_type) |
Matthias Fuchs | c6c882e | 2007-12-28 17:07:14 +0100 | [diff] [blame] | 54 | { |
| 55 | #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
| 56 | #if !defined(CONFIG_NAND_SPL) |
| 57 | ulong speed = get_bus_freq(0); |
| 58 | #else |
| 59 | ulong speed = 133333333; /* 133MHz is on the safe side */ |
| 60 | #endif |
| 61 | |
| 62 | mtsdram(DDR0_02, 0x00000000); |
| 63 | |
| 64 | mtsdram(DDR0_00, 0x0000190A); |
| 65 | mtsdram(DDR0_01, 0x01000000); |
| 66 | mtsdram(DDR0_03, 0x02030602); |
| 67 | mtsdram(DDR0_04, 0x0A020200); |
| 68 | mtsdram(DDR0_05, 0x02020308); |
| 69 | mtsdram(DDR0_06, 0x0102C812); |
| 70 | mtsdram(DDR0_07, 0x000D0100); |
| 71 | mtsdram(DDR0_08, 0x02430001); |
| 72 | mtsdram(DDR0_09, 0x00011D5F); |
| 73 | mtsdram(DDR0_10, 0x00000300); |
| 74 | mtsdram(DDR0_11, 0x0027C800); |
| 75 | mtsdram(DDR0_12, 0x00000003); |
| 76 | mtsdram(DDR0_14, 0x00000000); |
| 77 | mtsdram(DDR0_17, 0x19000000); |
| 78 | mtsdram(DDR0_18, 0x19191919); |
| 79 | mtsdram(DDR0_19, 0x19191919); |
| 80 | mtsdram(DDR0_20, 0x0B0B0B0B); |
| 81 | mtsdram(DDR0_21, 0x0B0B0B0B); |
| 82 | mtsdram(DDR0_22, 0x00267F0B); |
| 83 | mtsdram(DDR0_23, 0x00000000); |
| 84 | mtsdram(DDR0_24, 0x01010002); |
| 85 | if (speed > 133333334) |
| 86 | mtsdram(DDR0_26, 0x5B26050C); |
| 87 | else |
| 88 | mtsdram(DDR0_26, 0x5B260408); |
| 89 | mtsdram(DDR0_27, 0x0000682B); |
| 90 | mtsdram(DDR0_28, 0x00000000); |
| 91 | mtsdram(DDR0_31, 0x00000000); |
| 92 | mtsdram(DDR0_42, 0x01000006); |
| 93 | mtsdram(DDR0_43, 0x030A0200); |
| 94 | mtsdram(DDR0_44, 0x00000003); |
| 95 | mtsdram(DDR0_02, 0x00000001); |
| 96 | |
Matthias Fuchs | 88f4a7b | 2008-01-02 16:48:34 +0100 | [diff] [blame] | 97 | denali_wait_for_dlllock(); |
Matthias Fuchs | c6c882e | 2007-12-28 17:07:14 +0100 | [diff] [blame] | 98 | #endif /* #ifndef CONFIG_NAND_U_BOOT */ |
| 99 | |
| 100 | #ifdef CONFIG_DDR_DATA_EYE |
| 101 | /* -----------------------------------------------------------+ |
| 102 | * Perform data eye search if requested. |
| 103 | * ----------------------------------------------------------*/ |
Matthias Fuchs | 88f4a7b | 2008-01-02 16:48:34 +0100 | [diff] [blame] | 104 | denali_core_search_data_eye(); |
Matthias Fuchs | c6c882e | 2007-12-28 17:07:14 +0100 | [diff] [blame] | 105 | #endif |
| 106 | |
Matthias Fuchs | 640b9e7 | 2008-01-11 14:55:08 +0100 | [diff] [blame] | 107 | /* |
| 108 | * Clear possible errors resulting from data-eye-search. |
| 109 | * If not done, then we could get an interrupt later on when |
| 110 | * exceptions are enabled. |
| 111 | */ |
| 112 | set_mcsr(get_mcsr()); |
| 113 | |
Matthias Fuchs | c6c882e | 2007-12-28 17:07:14 +0100 | [diff] [blame] | 114 | return (CFG_MBYTES_SDRAM << 20); |
| 115 | } |