| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 8 | #include <asm-offsets.h> |
| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 9 | #include <ppc_asm.tmpl> |
| Stefan Roese | 94b6270 | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 10 | #include <asm/mmu.h> |
| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 11 | #include <config.h> |
| 12 | |
| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 13 | /************************************************************************** |
| 14 | * TLB TABLE |
| 15 | * |
| 16 | * This table is used by the cpu boot code to setup the initial tlb |
| 17 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 18 | * this table lets each board set things up however they like. |
| 19 | * |
| 20 | * Pointer to the table is returned in r1 |
| 21 | * |
| 22 | *************************************************************************/ |
| 23 | |
| 24 | .section .bootpg,"ax" |
| 25 | .globl tlbtab |
| 26 | |
| 27 | tlbtab: |
| Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 28 | tlbtab_start |
| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 29 | |
| Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 30 | /* |
| 31 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the |
| 32 | * speed up boot process. It is patched after relocation to enable SA_I |
| 33 | */ |
| Stefan Roese | 94b6270 | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 34 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/) |
| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 35 | |
| Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 36 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
| Stefan Roese | 94b6270 | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 37 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) |
| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 38 | |
| Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 39 | /* |
| 40 | * TLB entries for SDRAM are not needed on this platform. |
| 41 | * They are dynamically generated in the SPD DDR detection |
| 42 | * routine. |
| 43 | */ |
| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 44 | |
| Stefan Roese | 94b6270 | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 45 | tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG ) |
| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 46 | |
| Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 47 | /* PCI */ |
| Stefan Roese | 94b6270 | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 48 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG ) |
| 49 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG ) |
| 50 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG ) |
| 51 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG ) |
| Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 52 | |
| 53 | /* USB 2.0 Device */ |
| Stefan Roese | 94b6270 | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 54 | tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG ) |
| Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 55 | |
| Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 56 | tlbtab_end |