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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2001
3 * Stäubli Faverges - <www.staubli.com>
4 * Pierre AUBERT p.aubert@staubli.com
5 * U-Boot port on RPXClassic LF (CLLF_BW31) board
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <i2c.h>
31#include <config.h>
32#include <mpc8xx.h>
Heiko Schocher50219e62009-03-26 07:33:59 +010033#include <net.h>
wdenk5b1d7132002-11-03 00:07:02 +000034
35/* ------------------------------------------------------------------------- */
36
37static long int dram_size (long int, long int *, long int);
38static unsigned char aschex_to_byte (unsigned char *cp);
39
40/* ------------------------------------------------------------------------- */
41
42#define _NOT_USED_ 0xFFFFCC25
43
44const uint sdram_table[] =
45{
46 /*
47 * Single Read. (Offset 00h in UPMA RAM)
48 */
49 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
50 0x3FBFCC27, /* last */
51 _NOT_USED_, _NOT_USED_, _NOT_USED_,
52
53 /*
54 * Burst Read. (Offset 08h in UPMA RAM)
55 */
56 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
57 0x3FBFCC27, /* last */
58 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
60 _NOT_USED_, _NOT_USED_, _NOT_USED_,
61
62 /*
63 * Single Write. (Offset 18h in UPMA RAM)
64 */
65 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
66 0x3FFFCC27, /* last */
67 _NOT_USED_, _NOT_USED_, _NOT_USED_,
68
69 /*
70 * Burst Write. (Offset 20h in UPMA RAM)
71 */
72 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
73 0x0CFFCC00, 0x33FFCC27, /* last */
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 _NOT_USED_, _NOT_USED_,
77
78 /*
79 * Refresh. (Offset 30h in UPMA RAM)
80 */
81 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
82 0x3FFFCC27, /* last */
83 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
84 _NOT_USED_, _NOT_USED_, _NOT_USED_,
85
86 /*
87 * Exception. (Offset 3Ch in UPMA RAM)
88 */
89 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
90};
91
92/* ------------------------------------------------------------------------- */
93
94
95/*
96 * Check Board Identity:
97 */
98
99int checkboard (void)
100{
101 puts ("Board: RPXClassic\n");
102 return (0);
103}
104
105/*-----------------------------------------------------------------------------
106 * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
107 *-----------------------------------------------------------------------------
108 */
Mike Frysinger13e9bb92009-02-16 18:03:14 -0500109static void board_get_enetaddr(uchar *enet)
wdenk5b1d7132002-11-03 00:07:02 +0000110{
111 int i;
112 char buff[256], *cp;
113
114 /* Initialize I2C */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
wdenk5b1d7132002-11-03 00:07:02 +0000116
117 /* Read 256 bytes in EEPROM */
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200118 i2c_read (0x54, 0, 1, (uchar *)buff, 128);
119 i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
wdenk5b1d7132002-11-03 00:07:02 +0000120
121 /* Retrieve MAC address in buffer (key EA) */
122 for (cp = buff;;) {
123 if (cp[0] == 'E' && cp[1] == 'A') {
124 cp += 3;
125 /* Read MAC address */
126 for (i = 0; i < 6; i++, cp += 2) {
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200127 enet[i] = aschex_to_byte ((unsigned char *)cp);
wdenk5b1d7132002-11-03 00:07:02 +0000128 }
129 }
130 /* Scan to the end of the record */
wdenk67ff36c2002-11-19 23:01:07 +0000131 while ((*cp != '\n') && (*cp != (char)0xff)) {
wdenk5b1d7132002-11-03 00:07:02 +0000132 cp++;
133 }
134 /* If the next character is a \n, 0 or ff, we are done. */
135 cp++;
wdenk67ff36c2002-11-19 23:01:07 +0000136 if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff))
wdenk5b1d7132002-11-03 00:07:02 +0000137 break;
138 }
139
140#ifdef CONFIG_FEC_ENET
141 /* The MAC address is the same as normal ethernet except the 3rd byte */
142 /* (See the E.P. Planet Core Overview manual */
143 enet[3] |= 0x80;
wdenk5b1d7132002-11-03 00:07:02 +0000144#endif
145
Mike Frysinger13e9bb92009-02-16 18:03:14 -0500146 printf("MAC address = %pM\n", enet);
147}
148
149int misc_init_r(void)
150{
151 uchar enetaddr[6];
152
153 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
154 board_get_enetaddr(enetaddr);
Heiko Schocher50219e62009-03-26 07:33:59 +0100155 eth_setenv_enetaddr("ethaddr", enetaddr);
Mike Frysinger13e9bb92009-02-16 18:03:14 -0500156 }
wdenk5b1d7132002-11-03 00:07:02 +0000157
Mike Frysinger13e9bb92009-02-16 18:03:14 -0500158 return 0;
wdenk5b1d7132002-11-03 00:07:02 +0000159}
160
161void rpxclassic_init (void)
162{
163 /* Enable NVRAM */
164 *((uchar *) BCSR0) |= BCSR0_ENNVRAM;
165
wdenk67ff36c2002-11-19 23:01:07 +0000166#ifdef CONFIG_FEC_ENET
167
168 /* Validate the fast ethernet tranceiver */
169 *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
170 *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
171 *((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
172 *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
173#endif
174
wdenk5b1d7132002-11-03 00:07:02 +0000175}
176
177/* ------------------------------------------------------------------------- */
178
Becky Brucebd99ae72008-06-09 16:03:40 -0500179phys_size_t initdram (int board_type)
wdenk5b1d7132002-11-03 00:07:02 +0000180{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000182 volatile memctl8xx_t *memctl = &immap->im_memctl;
183 long int size10;
184
185 upmconfig (UPMA, (uint *) sdram_table,
186 sizeof (sdram_table) / sizeof (uint));
187
188 /* Refresh clock prescalar */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenk5b1d7132002-11-03 00:07:02 +0000190
191 memctl->memc_mar = 0x00000000;
192
193 /* Map controller banks 1 to the SDRAM bank */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
195 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
wdenk5b1d7132002-11-03 00:07:02 +0000196
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197 memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenk5b1d7132002-11-03 00:07:02 +0000198
199 udelay (200);
200
201 /* perform SDRAM initializsation sequence */
202
203 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
204 udelay (1);
205
206 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
207
208 udelay (1000);
209
210 /* Check Bank 0 Memory Size
211 * try 10 column mode
212 */
213
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214 size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
wdenk5b1d7132002-11-03 00:07:02 +0000215 SDRAM_MAX_SIZE);
216
217 return (size10);
218}
219
220/* ------------------------------------------------------------------------- */
221
222/*
223 * Check memory range for valid RAM. A simple memory test determines
224 * the actually available RAM size between addresses `base' and
225 * `base + maxsize'. Some (not all) hardware errors are detected:
226 * - short between address lines
227 * - short between data lines
228 */
229
230static long int dram_size (long int mamr_value, long int *base, long int maxsize)
231{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000233 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk5b1d7132002-11-03 00:07:02 +0000234
235 memctl->memc_mamr = mamr_value;
236
wdenk87249ba2004-01-06 22:38:14 +0000237 return (get_ram_size(base, maxsize));
wdenk5b1d7132002-11-03 00:07:02 +0000238}
wdenk67ff36c2002-11-19 23:01:07 +0000239/*-----------------------------------------------------------------------------
wdenk57b2d802003-06-27 21:31:46 +0000240 * aschex_to_byte --
wdenk67ff36c2002-11-19 23:01:07 +0000241 *-----------------------------------------------------------------------------
242 */
wdenk5b1d7132002-11-03 00:07:02 +0000243static unsigned char aschex_to_byte (unsigned char *cp)
244{
245 u_char byte, c;
246
247 c = *cp++;
248
249 if ((c >= 'A') && (c <= 'F')) {
250 c -= 'A';
251 c += 10;
252 } else if ((c >= 'a') && (c <= 'f')) {
253 c -= 'a';
254 c += 10;
255 } else {
256 c -= '0';
257 }
258
259 byte = c * 16;
260
261 c = *cp;
262
263 if ((c >= 'A') && (c <= 'F')) {
264 c -= 'A';
265 c += 10;
266 } else if ((c >= 'a') && (c <= 'f')) {
267 c -= 'a';
268 c += 10;
269 } else {
270 c -= '0';
271 }
272
273 byte += c;
274
275 return (byte);
276}