| TENART Antoine | 35c7e52 | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 1 | /* |
| 2 | * ti81xx.h |
| 3 | * |
| 4 | * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
| 5 | * Antoine Tenart, <atenart@adeneo-embedded.com> |
| 6 | * |
| 7 | * This file is released under the terms of GPL v2 and any later version. |
| 8 | * See the file COPYING in the root directory of the source tree for details. |
| 9 | */ |
| 10 | |
| 11 | #ifndef _CLOCK_TI81XX_H_ |
| 12 | #define _CLOCK_TI81XX_H_ |
| 13 | |
| 14 | #define PRCM_MOD_EN 0x2 |
| 15 | |
| 16 | #define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) |
| 17 | #define CM_ALWON_BASE (PRCM_BASE + 0x1400) |
| 18 | |
| 19 | struct cm_def { |
| 20 | unsigned int resv0[2]; |
| 21 | unsigned int l3fastclkstctrl; |
| 22 | unsigned int resv1[1]; |
| 23 | unsigned int pciclkstctrl; |
| 24 | unsigned int resv2[1]; |
| 25 | unsigned int ducaticlkstctrl; |
| 26 | unsigned int resv3[1]; |
| 27 | unsigned int emif0clkctrl; |
| 28 | unsigned int emif1clkctrl; |
| 29 | unsigned int dmmclkctrl; |
| 30 | unsigned int fwclkctrl; |
| 31 | unsigned int resv4[10]; |
| 32 | unsigned int usbclkctrl; |
| 33 | unsigned int resv5[1]; |
| 34 | unsigned int sataclkctrl; |
| 35 | unsigned int resv6[4]; |
| 36 | unsigned int ducaticlkctrl; |
| 37 | unsigned int pciclkctrl; |
| 38 | }; |
| 39 | |
| 40 | struct cm_alwon { |
| 41 | unsigned int l3slowclkstctrl; |
| 42 | unsigned int ethclkstctrl; |
| 43 | unsigned int l3medclkstctrl; |
| 44 | unsigned int mmu_clkstctrl; |
| 45 | unsigned int mmucfg_clkstctrl; |
| 46 | unsigned int ocmc0clkstctrl; |
| Tom Rini | 428deb3 | 2022-12-02 16:42:41 -0500 | [diff] [blame] | 47 | #if defined(CONFIG_TI816X) |
| TENART Antoine | 35c7e52 | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 48 | unsigned int ocmc1clkstctrl; |
| 49 | #endif |
| 50 | unsigned int mpuclkstctrl; |
| 51 | unsigned int sysclk4clkstctrl; |
| 52 | unsigned int sysclk5clkstctrl; |
| 53 | unsigned int sysclk6clkstctrl; |
| 54 | unsigned int rtcclkstctrl; |
| 55 | unsigned int l3fastclkstctrl; |
| 56 | unsigned int resv0[67]; |
| 57 | unsigned int mcasp0clkctrl; |
| 58 | unsigned int mcasp1clkctrl; |
| 59 | unsigned int mcasp2clkctrl; |
| 60 | unsigned int mcbspclkctrl; |
| 61 | unsigned int uart0clkctrl; |
| 62 | unsigned int uart1clkctrl; |
| 63 | unsigned int uart2clkctrl; |
| 64 | unsigned int gpio0clkctrl; |
| 65 | unsigned int gpio1clkctrl; |
| 66 | unsigned int i2c0clkctrl; |
| 67 | unsigned int i2c1clkctrl; |
| Tom Rini | 428deb3 | 2022-12-02 16:42:41 -0500 | [diff] [blame] | 68 | #if defined(CONFIG_TI816X) |
| TENART Antoine | 35c7e52 | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 69 | unsigned int resv1[1]; |
| 70 | unsigned int timer1clkctrl; |
| 71 | unsigned int timer2clkctrl; |
| 72 | unsigned int timer3clkctrl; |
| 73 | unsigned int timer4clkctrl; |
| 74 | unsigned int timer5clkctrl; |
| 75 | unsigned int timer6clkctrl; |
| 76 | unsigned int timer7clkctrl; |
| 77 | #endif |
| 78 | unsigned int wdtimerclkctrl; |
| 79 | unsigned int spiclkctrl; |
| 80 | unsigned int mailboxclkctrl; |
| 81 | unsigned int spinboxclkctrl; |
| 82 | unsigned int mmudataclkctrl; |
| 83 | unsigned int resv2[2]; |
| 84 | unsigned int mmucfgclkctrl; |
| Tom Rini | 428deb3 | 2022-12-02 16:42:41 -0500 | [diff] [blame] | 85 | #if defined(CONFIG_TI816X) |
| TENART Antoine | 35c7e52 | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 86 | unsigned int resv3[1]; |
| 87 | unsigned int sdioclkctrl; |
| 88 | #endif |
| 89 | unsigned int ocmc0clkctrl; |
| Tom Rini | 428deb3 | 2022-12-02 16:42:41 -0500 | [diff] [blame] | 90 | #if defined(CONFIG_TI816X) |
| TENART Antoine | 35c7e52 | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 91 | unsigned int ocmc1clkctrl; |
| 92 | #endif |
| 93 | unsigned int resv4[2]; |
| 94 | unsigned int controlclkctrl; |
| 95 | unsigned int resv5[2]; |
| 96 | unsigned int gpmcclkctrl; |
| 97 | unsigned int ethernet0clkctrl; |
| 98 | unsigned int ethernet1clkctrl; |
| 99 | unsigned int mpuclkctrl; |
| Tom Rini | 428deb3 | 2022-12-02 16:42:41 -0500 | [diff] [blame] | 100 | #if defined(CONFIG_TI816X) |
| TENART Antoine | 35c7e52 | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 101 | unsigned int resv6[1]; |
| 102 | #endif |
| 103 | unsigned int l3clkctrl; |
| 104 | unsigned int l4hsclkctrl; |
| 105 | unsigned int l4lsclkctrl; |
| 106 | unsigned int rtcclkctrl; |
| 107 | unsigned int tpccclkctrl; |
| 108 | unsigned int tptc0clkctrl; |
| 109 | unsigned int tptc1clkctrl; |
| 110 | unsigned int tptc2clkctrl; |
| 111 | unsigned int tptc3clkctrl; |
| Tom Rini | 428deb3 | 2022-12-02 16:42:41 -0500 | [diff] [blame] | 112 | #if defined(CONFIG_TI816X) |
| TENART Antoine | 35c7e52 | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 113 | unsigned int sr0clkctrl; |
| 114 | unsigned int sr1clkctrl; |
| 115 | #endif |
| 116 | }; |
| 117 | |
| 118 | #endif /* _CLOCK_TI81XX_H_ */ |