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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Fleming60ca78b2011-04-07 21:56:05 -05002/*
3 * Teranetics PHY drivers
4 *
Andy Fleming60ca78b2011-04-07 21:56:05 -05005 * Copyright 2010-2011 Freescale Semiconductor, Inc.
6 * author Andy Fleming
Andy Fleming60ca78b2011-04-07 21:56:05 -05007 */
Timur Tabia07b4972011-10-07 15:35:21 -05008#include <common.h>
Andy Fleming60ca78b2011-04-07 21:56:05 -05009#include <phy.h>
Simon Glassdbd79542020-05-10 11:40:11 -060010#include <linux/delay.h>
Andy Fleming60ca78b2011-04-07 21:56:05 -050011
12#ifndef CONFIG_PHYLIB_10G
13#error The Teranetics PHY needs 10G support
14#endif
15
16int tn2020_config(struct phy_device *phydev)
17{
18 if (phydev->port == PORT_FIBRE) {
19 unsigned short restart_an = (MDIO_AN_CTRL1_RESTART |
20 MDIO_AN_CTRL1_ENABLE |
21 MDIO_AN_CTRL1_XNP);
Shaohui Xie6bf9ec52013-03-25 07:39:59 +000022 u8 phy_hwversion;
Andy Fleming60ca78b2011-04-07 21:56:05 -050023
Shaohui Xie6bf9ec52013-03-25 07:39:59 +000024 /*
25 * bit 15:12 of register 30.32 indicates PHY hardware
26 * version. It can be used to distinguish TN80xx from
27 * TN2020. TN2020 needs write 0x2 to 30.93, but TN80xx
28 * needs 0x1.
29 */
30 phy_hwversion = (phy_read(phydev, 30, 32) >> 12) & 0xf;
31 if (phy_hwversion <= 3) {
32 phy_write(phydev, 30, 93, 2);
33 phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an);
34 } else {
35 phy_write(phydev, 30, 93, 1);
36 }
Andy Fleming60ca78b2011-04-07 21:56:05 -050037 }
38
39 return 0;
40}
41
Andy Fleming9d851742011-04-20 18:41:17 -050042int tn2020_startup(struct phy_device *phydev)
43{
Timur Tabia07b4972011-10-07 15:35:21 -050044 unsigned int timeout = 5 * 1000; /* 5 second timeout */
45
46#define MDIO_PHYXS_LANE_READY (MDIO_PHYXS_LNSTAT_SYNC0 | \
47 MDIO_PHYXS_LNSTAT_SYNC1 | \
48 MDIO_PHYXS_LNSTAT_SYNC2 | \
49 MDIO_PHYXS_LNSTAT_SYNC3 | \
50 MDIO_PHYXS_LNSTAT_ALIGN)
51
52 /*
53 * Wait for the XAUI-SERDES lanes to align first. Under normal
54 * circumstances, this can take up to three seconds.
55 */
56 while (--timeout) {
57 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT);
58 if (reg < 0) {
59 printf("TN2020: Error reading from PHY at "
60 "address %u\n", phydev->addr);
61 break;
62 }
63 if ((reg & MDIO_PHYXS_LANE_READY) == MDIO_PHYXS_LANE_READY)
64 break;
65 udelay(1000);
66 }
67 if (!timeout) {
68 /*
69 * A timeout is bad, but it may not be fatal, so don't
70 * return an error. Display a warning instead.
71 */
72 printf("TN2020: Timeout waiting for PHY at address %u to "
73 "align.\n", phydev->addr);
74 }
75
Andy Fleming9d851742011-04-20 18:41:17 -050076 if (phydev->port != PORT_FIBRE)
77 return gen10g_startup(phydev);
78
79 /*
80 * The TN2020 only pretends to support fiber.
81 * It works, but it doesn't look like it works,
82 * so the link status reports no link.
83 */
84 phydev->link = 1;
85
86 /* For now just lie and say it's 10G all the time */
87 phydev->speed = SPEED_10000;
88 phydev->duplex = DUPLEX_FULL;
89
90 return 0;
91}
92
Andy Fleming60ca78b2011-04-07 21:56:05 -050093struct phy_driver tn2020_driver = {
94 .name = "Teranetics TN2020",
Timur Tabi856f32f2011-10-18 18:44:34 -050095 .uid = PHY_UID_TN2020,
Andy Fleming60ca78b2011-04-07 21:56:05 -050096 .mask = 0xfffffff0,
97 .features = PHY_10G_FEATURES,
98 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
99 MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
100 MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
101 .config = &tn2020_config,
Andy Fleming9d851742011-04-20 18:41:17 -0500102 .startup = &tn2020_startup,
Andy Fleming60ca78b2011-04-07 21:56:05 -0500103 .shutdown = &gen10g_shutdown,
104};
105
106int phy_teranetics_init(void)
107{
108 phy_register(&tn2020_driver);
109
110 return 0;
111}