blob: d23a3942174d8aaad152b17f5da80fa057ceb1ce [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include <dt-bindings/phy/phy-imx8-pcie.h>
7#include <dt-bindings/pwm/pwm.h>
8#include "imx8mp.dtsi"
9
10/ {
11 chosen {
12 stdout-path = &uart3;
13 };
14
15 aliases {
16 /* Ethernet aliases to ensure correct MAC addresses */
17 ethernet0 = &eqos;
18 ethernet1 = &fec;
19 rtc0 = &rtc_i2c;
20 rtc1 = &snvs_rtc;
21 };
22
23 backlight: backlight {
24 compatible = "pwm-backlight";
25 brightness-levels = <0 45 63 88 119 158 203 255>;
26 default-brightness-level = <4>;
27 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
28 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
31 power-supply = <&reg_3p3v>;
32 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
33 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
34 status = "disabled";
35 };
36
37 backlight_mezzanine: backlight-mezzanine {
38 compatible = "pwm-backlight";
39 brightness-levels = <0 45 63 88 119 158 203 255>;
40 default-brightness-level = <4>;
41 /* Verdin GPIO 4 (SODIMM 212) */
42 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
43 /* Verdin PWM_2 (SODIMM 16) */
44 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
45 status = "disabled";
46 };
47
Tom Rini93743d22024-04-01 09:08:13 -040048 connector {
49 compatible = "gpio-usb-b-connector", "usb-b-connector";
50 id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
51 label = "Type-C";
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_usb_1_id>;
54 self-powered;
55 type = "micro";
56 vbus-supply = <&reg_usb1_vbus>;
57
58 port {
59 usb_dr_connector: endpoint {
60 remote-endpoint = <&usb3_dwc>;
61 };
62 };
63 };
64
Tom Rini53633a82024-02-29 12:33:36 -050065 gpio-keys {
66 compatible = "gpio-keys";
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_gpio_keys>;
69
70 key-wakeup {
71 debounce-interval = <10>;
72 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
73 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
74 label = "Wake-Up";
75 linux,code = <KEY_WAKEUP>;
76 wakeup-source;
77 };
78 };
79
80 /* Carrier Board Supplies */
81 reg_1p8v: regulator-1p8v {
82 compatible = "regulator-fixed";
83 regulator-max-microvolt = <1800000>;
84 regulator-min-microvolt = <1800000>;
85 regulator-name = "+V1.8_SW";
86 };
87
88 reg_3p3v: regulator-3p3v {
89 compatible = "regulator-fixed";
90 regulator-max-microvolt = <3300000>;
91 regulator-min-microvolt = <3300000>;
92 regulator-name = "+V3.3_SW";
93 };
94
95 reg_5p0v: regulator-5p0v {
96 compatible = "regulator-fixed";
97 regulator-max-microvolt = <5000000>;
98 regulator-min-microvolt = <5000000>;
99 regulator-name = "+V5_SW";
100 };
101
102 /* Non PMIC On-module Supplies */
103 reg_module_eth1phy: regulator-module-eth1phy {
104 compatible = "regulator-fixed";
105 enable-active-high;
106 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
107 off-on-delay-us = <500000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_reg_eth>;
110 regulator-always-on;
111 regulator-boot-on;
112 regulator-max-microvolt = <3300000>;
113 regulator-min-microvolt = <3300000>;
114 regulator-name = "On-module +V3.3_ETH";
115 startup-delay-us = <200000>;
116 vin-supply = <&reg_vdd_3v3>;
117 };
118
Tom Rini762f85b2024-07-20 11:15:10 -0600119 /*
120 * By default we enable CTRL_SLEEP_MOCI#, this is required to have
121 * peripherals on the carrier board powered.
122 * If more granularity or power saving is required this can be disabled
123 * in the carrier board device tree files.
124 */
125 reg_force_sleep_moci: regulator-force-sleep-moci {
126 compatible = "regulator-fixed";
127 enable-active-high;
128 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
129 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
130 regulator-always-on;
131 regulator-boot-on;
132 regulator-name = "CTRL_SLEEP_MOCI#";
133 };
134
Tom Rini53633a82024-02-29 12:33:36 -0500135 reg_usb1_vbus: regulator-usb1-vbus {
136 compatible = "regulator-fixed";
137 enable-active-high;
138 /* Verdin USB_1_EN (SODIMM 155) */
139 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_usb1_vbus>;
142 regulator-max-microvolt = <5000000>;
143 regulator-min-microvolt = <5000000>;
144 regulator-name = "USB_1_EN";
145 };
146
147 reg_usb2_vbus: regulator-usb2-vbus {
148 compatible = "regulator-fixed";
149 enable-active-high;
150 /* Verdin USB_2_EN (SODIMM 185) */
151 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_usb2_vbus>;
154 regulator-max-microvolt = <5000000>;
155 regulator-min-microvolt = <5000000>;
156 regulator-name = "USB_2_EN";
157 };
158
159 reg_usdhc2_vmmc: regulator-usdhc2 {
160 compatible = "regulator-fixed";
161 enable-active-high;
162 /* Verdin SD_1_PWR_EN (SODIMM 76) */
163 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
164 off-on-delay-us = <100000>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
167 regulator-max-microvolt = <3300000>;
168 regulator-min-microvolt = <3300000>;
169 regulator-name = "+V3.3_SD";
170 startup-delay-us = <2000>;
171 };
172
173 reserved-memory {
174 #address-cells = <2>;
175 #size-cells = <2>;
176 ranges;
177
178 /* Use the kernel configuration settings instead */
179 /delete-node/ linux,cma;
180 };
181};
182
183&A53_0 {
184 cpu-supply = <&reg_vdd_arm>;
185};
186
187&A53_1 {
188 cpu-supply = <&reg_vdd_arm>;
189};
190
191&A53_2 {
192 cpu-supply = <&reg_vdd_arm>;
193};
194
195&A53_3 {
196 cpu-supply = <&reg_vdd_arm>;
197};
198
199&cpu_alert0 {
200 temperature = <95000>;
201};
202
203&cpu_crit0 {
204 temperature = <105000>;
205};
206
207/* Verdin SPI_1 */
208&ecspi1 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_ecspi1>;
214};
215
216/* Verdin ETH_1 (On-module PHY) */
217&eqos {
218 phy-handle = <&ethphy0>;
219 phy-mode = "rgmii-id";
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_eqos>;
222 snps,force_thresh_dma_mode;
223 snps,mtl-rx-config = <&mtl_rx_setup>;
224 snps,mtl-tx-config = <&mtl_tx_setup>;
225
226 mdio {
227 compatible = "snps,dwmac-mdio";
228 #address-cells = <1>;
229 #size-cells = <0>;
230
231 ethphy0: ethernet-phy@7 {
232 compatible = "ethernet-phy-ieee802.3-c22";
233 eee-broken-100tx;
234 eee-broken-1000t;
235 interrupt-parent = <&gpio1>;
236 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
237 micrel,led-mode = <0>;
238 reg = <7>;
239 };
240 };
241
242 mtl_rx_setup: rx-queues-config {
243 snps,rx-queues-to-use = <5>;
Tom Rini53633a82024-02-29 12:33:36 -0500244
245 queue0 {
246 snps,dcb-algorithm;
247 snps,priority = <0x1>;
248 snps,map-to-dma-channel = <0>;
249 };
250
251 queue1 {
252 snps,dcb-algorithm;
253 snps,priority = <0x2>;
254 snps,map-to-dma-channel = <1>;
255 };
256
257 queue2 {
258 snps,dcb-algorithm;
259 snps,priority = <0x4>;
260 snps,map-to-dma-channel = <2>;
261 };
262
263 queue3 {
264 snps,dcb-algorithm;
265 snps,priority = <0x8>;
266 snps,map-to-dma-channel = <3>;
267 };
268
269 queue4 {
270 snps,dcb-algorithm;
271 snps,priority = <0xf0>;
272 snps,map-to-dma-channel = <4>;
273 };
274 };
275
276 mtl_tx_setup: tx-queues-config {
277 snps,tx-queues-to-use = <5>;
Tom Rini53633a82024-02-29 12:33:36 -0500278
279 queue0 {
280 snps,dcb-algorithm;
281 snps,priority = <0x1>;
282 };
283
284 queue1 {
285 snps,dcb-algorithm;
286 snps,priority = <0x2>;
287 };
288
289 queue2 {
290 snps,dcb-algorithm;
291 snps,priority = <0x4>;
292 };
293
294 queue3 {
295 snps,dcb-algorithm;
296 snps,priority = <0x8>;
297 };
298
299 queue4 {
300 snps,dcb-algorithm;
301 snps,priority = <0xf0>;
302 };
303 };
304};
305
306/* Verdin ETH_2_RGMII */
307&fec {
308 fsl,magic-packet;
309 phy-handle = <&ethphy1>;
310 phy-mode = "rgmii-id";
311 pinctrl-names = "default", "sleep";
312 pinctrl-0 = <&pinctrl_fec>;
313 pinctrl-1 = <&pinctrl_fec_sleep>;
314
315 mdio {
316 #address-cells = <1>;
317 #size-cells = <0>;
318
319 ethphy1: ethernet-phy@7 {
320 compatible = "ethernet-phy-ieee802.3-c22";
321 interrupt-parent = <&gpio4>;
322 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
323 micrel,led-mode = <0>;
324 reg = <7>;
325 };
326 };
327};
328
329/* Verdin CAN_1 */
330&flexcan1 {
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_flexcan1>;
333 status = "disabled";
334};
335
336/* Verdin CAN_2 */
337&flexcan2 {
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_flexcan2>;
340 status = "disabled";
341};
342
343/* Verdin QSPI_1 */
344&flexspi {
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_flexspi0>;
347};
348
349&gpio1 {
350 gpio-line-names = "SODIMM_206",
351 "SODIMM_208",
352 "",
353 "",
354 "",
355 "SODIMM_210",
356 "SODIMM_212",
357 "SODIMM_216",
358 "SODIMM_218",
359 "",
360 "",
361 "SODIMM_16",
362 "SODIMM_155",
363 "SODIMM_157",
364 "SODIMM_185",
365 "SODIMM_91";
366};
367
368&gpio2 {
369 gpio-line-names = "",
370 "",
371 "",
372 "",
373 "",
374 "",
375 "SODIMM_143",
376 "SODIMM_141",
377 "",
378 "",
379 "SODIMM_161",
380 "",
381 "SODIMM_84",
382 "SODIMM_78",
383 "SODIMM_74",
384 "SODIMM_80",
385 "SODIMM_82",
386 "SODIMM_70",
387 "SODIMM_72";
388};
389
390&gpio3 {
391 gpio-line-names = "SODIMM_52",
392 "SODIMM_54",
393 "",
394 "",
395 "",
396 "",
397 "SODIMM_56",
398 "SODIMM_58",
399 "SODIMM_60",
400 "SODIMM_62",
401 "",
402 "",
403 "",
404 "",
405 "SODIMM_66",
406 "",
407 "SODIMM_64",
408 "",
409 "",
410 "SODIMM_34",
411 "SODIMM_19",
412 "",
413 "SODIMM_32",
414 "",
415 "",
416 "SODIMM_30",
417 "SODIMM_59",
418 "SODIMM_57",
419 "SODIMM_63",
420 "SODIMM_61";
421};
422
423&gpio4 {
424 gpio-line-names = "SODIMM_252",
425 "SODIMM_222",
426 "SODIMM_36",
427 "SODIMM_220",
428 "SODIMM_193",
429 "SODIMM_191",
430 "SODIMM_201",
431 "SODIMM_203",
432 "SODIMM_205",
433 "SODIMM_207",
434 "SODIMM_199",
435 "SODIMM_197",
436 "SODIMM_221",
437 "SODIMM_219",
438 "SODIMM_217",
439 "SODIMM_215",
440 "SODIMM_211",
441 "SODIMM_213",
442 "SODIMM_189",
443 "SODIMM_244",
444 "SODIMM_38",
445 "",
446 "SODIMM_76",
447 "SODIMM_135",
448 "SODIMM_133",
449 "SODIMM_17",
450 "SODIMM_24",
451 "SODIMM_26",
452 "SODIMM_21",
453 "SODIMM_256",
454 "SODIMM_48",
455 "SODIMM_44";
Tom Rini53633a82024-02-29 12:33:36 -0500456};
457
Tom Rini6b642ac2024-10-01 12:20:28 -0600458/* Verdin HDMI_1 */
459&hdmi_tx {
460 ddc-i2c-bus = <&i2c5>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_hdmi>;
463};
464
Tom Rini53633a82024-02-29 12:33:36 -0500465/* On-module I2C */
466&i2c1 {
467 clock-frequency = <400000>;
468 pinctrl-names = "default", "gpio";
469 pinctrl-0 = <&pinctrl_i2c1>;
470 pinctrl-1 = <&pinctrl_i2c1_gpio>;
471 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
472 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
473 status = "okay";
474
475 pca9450: pmic@25 {
476 compatible = "nxp,pca9450c";
477 interrupt-parent = <&gpio1>;
478 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
479 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_pmic>;
482 reg = <0x25>;
483
484 /*
485 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
486 * I2C level shifter for the TLA2024 ADC behind this PMIC.
487 */
488
489 regulators {
490 BUCK1 {
491 regulator-always-on;
492 regulator-boot-on;
493 regulator-max-microvolt = <1000000>;
494 regulator-min-microvolt = <720000>;
495 regulator-name = "On-module +VDD_SOC (BUCK1)";
496 regulator-ramp-delay = <3125>;
497 };
498
499 reg_vdd_arm: BUCK2 {
500 nxp,dvs-run-voltage = <950000>;
501 nxp,dvs-standby-voltage = <850000>;
502 regulator-always-on;
503 regulator-boot-on;
504 regulator-max-microvolt = <1025000>;
505 regulator-min-microvolt = <720000>;
506 regulator-name = "On-module +VDD_ARM (BUCK2)";
507 regulator-ramp-delay = <3125>;
508 };
509
510 reg_vdd_3v3: BUCK4 {
511 regulator-always-on;
512 regulator-boot-on;
513 regulator-max-microvolt = <3300000>;
514 regulator-min-microvolt = <3300000>;
515 regulator-name = "On-module +V3.3 (BUCK4)";
516 };
517
518 reg_vdd_1v8: BUCK5 {
519 regulator-always-on;
520 regulator-boot-on;
521 regulator-max-microvolt = <1800000>;
522 regulator-min-microvolt = <1800000>;
523 regulator-name = "PWR_1V8_MOCI (BUCK5)";
524 };
525
526 BUCK6 {
527 regulator-always-on;
528 regulator-boot-on;
529 regulator-max-microvolt = <1155000>;
530 regulator-min-microvolt = <1045000>;
531 regulator-name = "On-module +VDD_DDR (BUCK6)";
532 };
533
534 LDO1 {
535 regulator-always-on;
536 regulator-boot-on;
537 regulator-max-microvolt = <1950000>;
538 regulator-min-microvolt = <1650000>;
539 regulator-name = "On-module +V1.8_SNVS (LDO1)";
540 };
541
542 LDO2 {
543 regulator-always-on;
544 regulator-boot-on;
545 regulator-max-microvolt = <1150000>;
546 regulator-min-microvolt = <800000>;
547 regulator-name = "On-module +V0.8_SNVS (LDO2)";
548 };
549
550 LDO3 {
551 regulator-always-on;
552 regulator-boot-on;
553 regulator-max-microvolt = <1800000>;
554 regulator-min-microvolt = <1800000>;
555 regulator-name = "On-module +V1.8A (LDO3)";
556 };
557
558 LDO4 {
559 regulator-always-on;
560 regulator-boot-on;
561 regulator-max-microvolt = <3300000>;
562 regulator-min-microvolt = <3300000>;
563 regulator-name = "On-module +V3.3_ADC (LDO4)";
564 };
565
Tom Rini6bb92fc2024-05-20 09:54:58 -0600566 reg_vdd_sdio: LDO5 {
Tom Rini53633a82024-02-29 12:33:36 -0500567 regulator-max-microvolt = <3300000>;
568 regulator-min-microvolt = <1800000>;
569 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
570 };
571 };
572 };
573
574 rtc_i2c: rtc@32 {
575 compatible = "epson,rx8130";
576 reg = <0x32>;
577 };
578
579 /* On-module temperature sensor */
580 hwmon_temp_module: sensor@48 {
581 compatible = "ti,tmp1075";
582 reg = <0x48>;
583 vs-supply = <&reg_vdd_1v8>;
584 };
585
586 adc@49 {
587 compatible = "ti,ads1015";
588 reg = <0x49>;
589 #address-cells = <1>;
590 #size-cells = <0>;
591
592 /* Verdin I2C_1 (ADC_4 - ADC_3) */
593 channel@0 {
594 reg = <0>;
595 ti,datarate = <4>;
596 ti,gain = <2>;
597 };
598
599 /* Verdin I2C_1 (ADC_4 - ADC_1) */
600 channel@1 {
601 reg = <1>;
602 ti,datarate = <4>;
603 ti,gain = <2>;
604 };
605
606 /* Verdin I2C_1 (ADC_3 - ADC_1) */
607 channel@2 {
608 reg = <2>;
609 ti,datarate = <4>;
610 ti,gain = <2>;
611 };
612
613 /* Verdin I2C_1 (ADC_2 - ADC_1) */
614 channel@3 {
615 reg = <3>;
616 ti,datarate = <4>;
617 ti,gain = <2>;
618 };
619
620 /* Verdin I2C_1 ADC_4 */
621 channel@4 {
622 reg = <4>;
623 ti,datarate = <4>;
624 ti,gain = <2>;
625 };
626
627 /* Verdin I2C_1 ADC_3 */
628 channel@5 {
629 reg = <5>;
630 ti,datarate = <4>;
631 ti,gain = <2>;
632 };
633
634 /* Verdin I2C_1 ADC_2 */
635 channel@6 {
636 reg = <6>;
637 ti,datarate = <4>;
638 ti,gain = <2>;
639 };
640
641 /* Verdin I2C_1 ADC_1 */
642 channel@7 {
643 reg = <7>;
644 ti,datarate = <4>;
645 ti,gain = <2>;
646 };
647 };
648
649 eeprom@50 {
650 compatible = "st,24c02";
651 pagesize = <16>;
652 reg = <0x50>;
653 };
654};
655
656/* Verdin I2C_2_DSI */
657&i2c2 {
Tom Rini6b642ac2024-10-01 12:20:28 -0600658 clock-frequency = <400000>;
Tom Rini53633a82024-02-29 12:33:36 -0500659 pinctrl-names = "default", "gpio";
660 pinctrl-0 = <&pinctrl_i2c2>;
661 pinctrl-1 = <&pinctrl_i2c2_gpio>;
662 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
663 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
664
665 atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
666 compatible = "atmel,maxtouch";
667 /* Verdin GPIO_3 (SODIMM 210) */
668 interrupt-parent = <&gpio1>;
669 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
670 reg = <0x4a>;
671 /* Verdin GPIO_2 (SODIMM 208) */
672 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
673 status = "disabled";
674 };
675};
676
Tom Rini53633a82024-02-29 12:33:36 -0500677/* Verdin I2C_4_CSI */
678&i2c3 {
679 clock-frequency = <400000>;
680 pinctrl-names = "default", "gpio";
681 pinctrl-0 = <&pinctrl_i2c3>;
682 pinctrl-1 = <&pinctrl_i2c3_gpio>;
683 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
684 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
685};
686
687/* Verdin I2C_1 */
688&i2c4 {
689 clock-frequency = <400000>;
690 pinctrl-names = "default", "gpio";
691 pinctrl-0 = <&pinctrl_i2c4>;
692 pinctrl-1 = <&pinctrl_i2c4_gpio>;
693 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
694 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
695
696 gpio_expander_21: gpio-expander@21 {
697 compatible = "nxp,pcal6416";
698 #gpio-cells = <2>;
699 gpio-controller;
700 reg = <0x21>;
701 vcc-supply = <&reg_3p3v>;
702 status = "disabled";
703 };
704
705 lvds_ti_sn65dsi84: bridge@2c {
706 compatible = "ti,sn65dsi84";
707 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
708 /* Verdin GPIO_10_DSI (SODIMM 21) */
709 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
710 pinctrl-names = "default";
711 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
712 reg = <0x2c>;
713 status = "disabled";
714 };
715
716 /* Current measurement into module VCC */
717 hwmon: hwmon@40 {
718 compatible = "ti,ina219";
719 reg = <0x40>;
720 shunt-resistor = <10000>;
721 status = "disabled";
722 };
723
724 hdmi_lontium_lt8912: hdmi@48 {
725 compatible = "lontium,lt8912b";
726 pinctrl-names = "default";
727 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
728 reg = <0x48>;
729 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
730 /* Verdin GPIO_10_DSI (SODIMM 21) */
731 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
732 status = "disabled";
733 };
734
735 atmel_mxt_ts: touch@4a {
736 compatible = "atmel,maxtouch";
737 /*
738 * Verdin GPIO_9_DSI
739 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
740 */
741 interrupt-parent = <&gpio4>;
742 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
743 pinctrl-names = "default";
744 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
745 reg = <0x4a>;
746 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
747 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
748 status = "disabled";
749 };
750
751 /* Temperature sensor on carrier board */
752 hwmon_temp: sensor@4f {
753 compatible = "ti,tmp75c";
754 reg = <0x4f>;
755 status = "disabled";
756 };
757
758 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
759 eeprom_display_adapter: eeprom@50 {
760 compatible = "st,24c02";
761 pagesize = <16>;
762 reg = <0x50>;
763 status = "disabled";
764 };
765
766 /* EEPROM on carrier board */
767 eeprom_carrier_board: eeprom@57 {
768 compatible = "st,24c02";
769 pagesize = <16>;
770 reg = <0x57>;
771 status = "disabled";
772 };
773};
774
Tom Rini762f85b2024-07-20 11:15:10 -0600775/* Verdin I2C_3_HDMI */
776&i2c5 {
777 clock-frequency = <100000>;
778 pinctrl-names = "default", "gpio";
779 pinctrl-0 = <&pinctrl_i2c5>;
780 pinctrl-1 = <&pinctrl_i2c5_gpio>;
781 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
782 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
783};
784
Tom Rini53633a82024-02-29 12:33:36 -0500785/* Verdin PCIE_1 */
786&pcie {
787 pinctrl-names = "default";
788 pinctrl-0 = <&pinctrl_pcie>;
789 /* PCIE_1_RESET# (SODIMM 244) */
790 reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
791};
792
793&pcie_phy {
794 clocks = <&hsio_blk_ctrl>;
795 clock-names = "ref";
796 fsl,clkreq-unsupported;
797 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
798};
799
800/* Verdin PWM_1 */
801&pwm1 {
802 pinctrl-names = "default";
803 pinctrl-0 = <&pinctrl_pwm_1>;
804 #pwm-cells = <3>;
805};
806
807/* Verdin PWM_2 */
808&pwm2 {
809 pinctrl-names = "default";
810 pinctrl-0 = <&pinctrl_pwm_2>;
811 #pwm-cells = <3>;
812};
813
814/* Verdin PWM_3_DSI */
815&pwm3 {
816 pinctrl-names = "default";
817 pinctrl-0 = <&pinctrl_pwm_3>;
818 #pwm-cells = <3>;
819};
820
821/* TODO: Verdin I2S_1 */
822
823/* TODO: Verdin I2S_2 */
824
825&snvs_pwrkey {
826 status = "okay";
827};
828
829/* Verdin UART_1 */
830&uart1 {
831 pinctrl-names = "default";
832 pinctrl-0 = <&pinctrl_uart1>;
833 uart-has-rtscts;
834};
835
836/* Verdin UART_2 */
837&uart2 {
838 pinctrl-names = "default";
839 pinctrl-0 = <&pinctrl_uart2>;
840 uart-has-rtscts;
841};
842
843/* Verdin UART_3, used as the Linux Console */
844&uart3 {
845 pinctrl-names = "default";
846 pinctrl-0 = <&pinctrl_uart3>;
847};
848
849/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
850&uart4 {
851 pinctrl-names = "default";
852 pinctrl-0 = <&pinctrl_uart4>;
853};
854
855/* Verdin USB_1 */
856&usb3_0 {
857 fsl,disable-port-power-control;
858 fsl,over-current-active-low;
859 pinctrl-names = "default";
860 pinctrl-0 = <&pinctrl_usb_1_oc_n>;
861};
862
863&usb_dwc3_0 {
864 /* dual role only, not full featured OTG */
865 adp-disable;
866 dr_mode = "otg";
867 hnp-disable;
868 maximum-speed = "high-speed";
869 role-switch-default-mode = "peripheral";
870 srp-disable;
871 usb-role-switch;
872
Tom Rini93743d22024-04-01 09:08:13 -0400873 port {
874 usb3_dwc: endpoint {
875 remote-endpoint = <&usb_dr_connector>;
876 };
Tom Rini53633a82024-02-29 12:33:36 -0500877 };
878};
879
880/* Verdin USB_2 */
881&usb3_1 {
882 fsl,disable-port-power-control;
883};
884
885&usb3_phy1 {
886 vbus-supply = <&reg_usb2_vbus>;
887};
888
889&usb_dwc3_1 {
890 dr_mode = "host";
891};
892
893/* Verdin SD_1 */
894&usdhc2 {
895 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
896 assigned-clock-rates = <400000000>;
897 bus-width = <4>;
898 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
899 disable-wp;
900 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
901 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
902 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
903 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
904 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
905 vmmc-supply = <&reg_usdhc2_vmmc>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600906 vqmmc-supply = <&reg_vdd_sdio>;
Tom Rini53633a82024-02-29 12:33:36 -0500907};
908
909/* On-module eMMC */
910&usdhc3 {
911 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
912 assigned-clock-rates = <400000000>;
913 bus-width = <8>;
914 non-removable;
915 pinctrl-names = "default", "state_100mhz", "state_200mhz";
916 pinctrl-0 = <&pinctrl_usdhc3>;
917 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
918 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
919 status = "okay";
920};
921
922&wdog1 {
923 fsl,ext-reset-output;
924 pinctrl-names = "default";
925 pinctrl-0 = <&pinctrl_wdog>;
926 status = "okay";
927};
928
929&iomuxc {
930 pinctrl_bt_uart: btuartgrp {
931 fsl,pins =
932 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>,
933 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>,
934 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>,
935 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>;
936 };
937
938 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
939 fsl,pins =
940 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */
941 };
942
943 pinctrl_ecspi1: ecspi1grp {
944 fsl,pins =
945 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */
946 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */
947 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */
948 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */
949 };
950
951 /* Connection On Board PHY */
952 pinctrl_eqos: eqosgrp {
953 fsl,pins =
954 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
955 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
956 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
957 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
958 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
959 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
960 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
961 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
962 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
963 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
964 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
965 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
966 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
967 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
968 };
969
970 /* ETH_INT# shared with TPM_INT# (usually N/A) */
971 pinctrl_eth_tpm_int: ethtpmintgrp {
972 fsl,pins =
973 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>;
974 };
975
976 /* Connection Carrier Board PHY ETH_2 */
977 pinctrl_fec: fecgrp {
978 fsl,pins =
979 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
980 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
981 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
982 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
983 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
984 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
985 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
986 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
987 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */
988 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */
989 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */
990 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */
991 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */
992 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */
993 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */
994 };
995
996 pinctrl_fec_sleep: fecsleepgrp {
997 fsl,pins =
998 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
999 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
1000 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
1001 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
1002 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
1003 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
1004 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
1005 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
1006 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */
1007 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */
1008 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */
1009 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */
1010 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */
1011 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */
1012 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */
1013 };
1014
1015 pinctrl_flexcan1: flexcan1grp {
1016 fsl,pins =
1017 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */
1018 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */
1019 };
1020
1021 pinctrl_flexcan2: flexcan2grp {
1022 fsl,pins =
1023 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */
1024 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */
1025 };
1026
1027 pinctrl_flexspi0: flexspi0grp {
1028 fsl,pins =
1029 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
1030 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */
1031 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */
1032 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */
1033 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */
1034 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */
1035 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */
1036 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */
1037 };
1038
1039 pinctrl_gpio1: gpio1grp {
1040 fsl,pins =
1041 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */
1042 };
1043
1044 pinctrl_gpio2: gpio2grp {
1045 fsl,pins =
1046 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */
1047 };
1048
1049 pinctrl_gpio3: gpio3grp {
1050 fsl,pins =
1051 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */
1052 };
1053
1054 pinctrl_gpio4: gpio4grp {
1055 fsl,pins =
1056 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */
1057 };
1058
1059 pinctrl_gpio5: gpio5grp {
1060 fsl,pins =
1061 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */
1062 };
1063
1064 pinctrl_gpio6: gpio6grp {
1065 fsl,pins =
1066 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */
1067 };
1068
1069 pinctrl_gpio7: gpio7grp {
1070 fsl,pins =
1071 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */
1072 };
1073
1074 pinctrl_gpio8: gpio8grp {
1075 fsl,pins =
1076 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */
1077 };
1078
1079 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
1080 pinctrl_gpio_9_dsi: gpio9dsigrp {
1081 fsl,pins =
1082 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */
1083 };
1084
1085 /* Verdin GPIO_10_DSI */
1086 pinctrl_gpio_10_dsi: gpio10dsigrp {
1087 fsl,pins =
1088 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */
1089 };
1090
1091 /* Non-wifi MSP usage only */
1092 pinctrl_gpio_hog1: gpiohog1grp {
1093 fsl,pins =
1094 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */
1095 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */
1096 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */
1097 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */
1098 };
1099
1100 /* USB_2_OC# */
1101 pinctrl_gpio_hog2: gpiohog2grp {
1102 fsl,pins =
1103 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */
1104 };
1105
1106 pinctrl_gpio_hog3: gpiohog3grp {
1107 fsl,pins =
1108 /* CSI_1_MCLK */
1109 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
1110 };
1111
1112 /* Wifi usage only */
1113 pinctrl_gpio_hog4: gpiohog4grp {
1114 fsl,pins =
1115 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */
1116 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */
1117 };
1118
1119 pinctrl_gpio_keys: gpiokeysgrp {
1120 fsl,pins =
1121 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */
1122 };
1123
Tom Rini6b642ac2024-10-01 12:20:28 -06001124 pinctrl_hdmi: hdmigrp {
Tom Rini53633a82024-02-29 12:33:36 -05001125 fsl,pins =
Tom Rini6b642ac2024-10-01 12:20:28 -06001126 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x140>, /* SODIMM 63 */
1127 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x180>; /* SODIMM 61 */
Tom Rini53633a82024-02-29 12:33:36 -05001128 };
1129
1130 /* On-module I2C */
1131 pinctrl_i2c1: i2c1grp {
1132 fsl,pins =
1133 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
1134 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
1135 };
1136
1137 pinctrl_i2c1_gpio: i2c1gpiogrp {
1138 fsl,pins =
1139 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
1140 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
1141 };
1142
1143 /* Verdin I2C_2_DSI */
1144 pinctrl_i2c2: i2c2grp {
1145 fsl,pins =
1146 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */
1147 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */
1148 };
1149
1150 pinctrl_i2c2_gpio: i2c2gpiogrp {
1151 fsl,pins =
1152 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
1153 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
1154 };
1155
1156 /* Verdin I2C_4_CSI */
1157 pinctrl_i2c3: i2c3grp {
1158 fsl,pins =
1159 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */
1160 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */
1161 };
1162
1163 pinctrl_i2c3_gpio: i2c3gpiogrp {
1164 fsl,pins =
1165 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
1166 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
1167 };
1168
1169 /* Verdin I2C_1 */
1170 pinctrl_i2c4: i2c4grp {
1171 fsl,pins =
1172 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */
1173 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */
1174 };
1175
1176 pinctrl_i2c4_gpio: i2c4gpiogrp {
1177 fsl,pins =
1178 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
1179 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
1180 };
1181
Tom Rini762f85b2024-07-20 11:15:10 -06001182 /* Verdin I2C_3_HDMI */
1183 pinctrl_i2c5: i2c5grp {
1184 fsl,pins =
1185 <MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400001c6>, /* SODIMM 59 */
1186 <MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400001c6>; /* SODIMM 57 */
1187 };
1188
1189 pinctrl_i2c5_gpio: i2c5gpiogrp {
1190 fsl,pins =
1191 <MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x400001c6>, /* SODIMM 59 */
1192 <MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x400001c6>; /* SODIMM 57 */
1193 };
1194
Tom Rini53633a82024-02-29 12:33:36 -05001195 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1196 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1197 fsl,pins =
1198 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */
1199 };
1200
1201 /* Verdin I2S_2_D_OUT shared with SAI3 */
1202 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1203 fsl,pins =
1204 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */
1205 };
1206
1207 pinctrl_pcie: pciegrp {
1208 fsl,pins =
1209 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */
1210 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */
1211 };
1212
1213 pinctrl_pmic: pmicirqgrp {
1214 fsl,pins =
1215 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
1216 };
1217
1218 pinctrl_pwm_1: pwm1grp {
1219 fsl,pins =
1220 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */
1221 };
1222
1223 pinctrl_pwm_2: pwm2grp {
1224 fsl,pins =
1225 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */
1226 };
1227
1228 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */
1229 pinctrl_pwm_3: pwm3grp {
1230 fsl,pins =
1231 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */
1232 };
1233
1234 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
1235 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
1236 fsl,pins =
1237 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */
1238 };
1239
1240 pinctrl_reg_eth: regethgrp {
1241 fsl,pins =
1242 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
1243 };
1244
1245 pinctrl_sai1: sai1grp {
1246 fsl,pins =
1247 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */
1248 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */
1249 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */
1250 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */
1251 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */
1252 };
1253
1254 pinctrl_sai3: sai3grp {
1255 fsl,pins =
1256 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */
1257 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */
1258 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */
1259 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */
1260 };
1261
1262 pinctrl_uart1: uart1grp {
1263 fsl,pins =
1264 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */
1265 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */
1266 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */
1267 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */
1268 };
1269
1270 pinctrl_uart2: uart2grp {
1271 fsl,pins =
1272 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */
1273 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */
1274 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */
1275 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */
1276 };
1277
1278 pinctrl_uart3: uart3grp {
1279 fsl,pins =
1280 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */
1281 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */
1282 };
1283
1284 /* Non-wifi usage only */
1285 pinctrl_uart4: uart4grp {
1286 fsl,pins =
1287 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
1288 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
1289 };
1290
1291 pinctrl_usb1_vbus: usb1vbusgrp {
1292 fsl,pins =
1293 <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */
1294 };
1295
1296 /* USB_1_ID */
1297 pinctrl_usb_1_id: usb1idgrp {
1298 fsl,pins =
1299 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
1300 };
1301
1302 /* USB_1_OC# */
1303 pinctrl_usb_1_oc_n: usb1ocngrp {
1304 fsl,pins =
1305 <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */
1306 };
1307
1308 pinctrl_usb2_vbus: usb2vbusgrp {
1309 fsl,pins =
1310 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */
1311 };
1312
1313 /* On-module Wi-Fi */
1314 pinctrl_usdhc1: usdhc1grp {
1315 fsl,pins =
1316 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>,
1317 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>,
1318 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>,
1319 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>,
1320 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>,
1321 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>;
1322 };
1323
1324 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1325 fsl,pins =
1326 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>,
1327 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>,
1328 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>,
1329 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>,
1330 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>,
1331 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>;
1332 };
1333
1334 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1335 fsl,pins =
1336 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>,
1337 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>,
1338 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>,
1339 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>,
1340 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>,
1341 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>;
1342 };
1343
1344 pinctrl_usdhc2_cd: usdhc2cdgrp {
1345 fsl,pins =
1346 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */
1347 };
1348
1349 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1350 fsl,pins =
1351 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */
1352 };
1353
1354 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1355 fsl,pins =
1356 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */
1357 };
1358
1359 pinctrl_usdhc2: usdhc2grp {
1360 fsl,pins =
1361 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */
1362 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */
1363 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */
1364 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
1365 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
1366 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
1367 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */
1368 };
1369
1370 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1371 fsl,pins =
1372 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1373 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
1374 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
1375 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
1376 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
1377 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
1378 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
1379 };
1380
1381 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1382 fsl,pins =
1383 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1384 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
1385 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
1386 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
1387 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
1388 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
1389 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>;
1390 };
1391
1392 /* Avoid backfeeding with removed card power */
1393 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1394 fsl,pins =
1395 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>,
1396 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>,
1397 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>,
1398 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>,
1399 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>,
1400 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>,
1401 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>;
1402 };
1403
1404 pinctrl_usdhc3: usdhc3grp {
1405 fsl,pins =
1406 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1407 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>,
1408 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
1409 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
1410 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
1411 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
1412 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
1413 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
1414 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
1415 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
1416 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
1417 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>;
1418 };
1419
1420 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1421 fsl,pins =
1422 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1423 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>,
1424 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
1425 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
1426 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
1427 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
1428 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
1429 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
1430 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
1431 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
1432 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
1433 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>;
1434 };
1435
1436 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1437 fsl,pins =
1438 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1439 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>,
1440 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>,
1441 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>,
1442 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>,
1443 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>,
1444 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>,
1445 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>,
1446 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>,
1447 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>,
1448 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
1449 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>;
1450 };
1451
1452 pinctrl_wdog: wdoggrp {
1453 fsl,pins =
1454 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
1455 };
1456
1457 pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
1458 fsl,pins =
1459 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */
1460 };
1461
1462 pinctrl_wifi_ctrl: wifictrlgrp {
1463 fsl,pins =
1464 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */
1465 };
1466
1467 pinctrl_wifi_i2s: wifii2sgrp {
1468 fsl,pins =
1469 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */
1470 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */
1471 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */
1472 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */
1473 };
1474
1475 pinctrl_wifi_pwr_en: wifipwrengrp {
1476 fsl,pins =
1477 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */
1478 };
1479};