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git01.mediatek.com / filogic / uboot / dd2600e5708b4a1a6d60962ee0e12fa2b11c0860 / . / dts / upstream / src / arm64 / freescale / imx8mm-beacon-baseboard.dtsi
blob: 6086dae2e5fbef37e9a583860b6fa9af57970e76 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
6#include <dt-bindings/phy/phy-imx8-pcie.h>
7
8/ {
9
10 dmic_codec: dmic-codec {
11 compatible = "dmic-codec";
12 num-channels = <1>;
13 #sound-dai-cells = <0>;
14 };
15
16 leds {
17 compatible = "gpio-leds";
18
19 led0 {
20 label = "gen_led0";
21 gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
22 default-state = "off";
23 };
24
25 led1 {
26 label = "gen_led1";
27 gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
28 default-state = "off";
29 };
30
31 led2 {
32 label = "gen_led2";
33 gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
34 default-state = "off";
35 };
36
37 led3 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_led3>;
40 label = "heartbeat";
41 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
42 linux,default-trigger = "heartbeat";
43 };
44 };
45
46 pcie0_refclk: pcie0-refclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <100000000>;
50 };
51
52 pcie0_refclk_gated: pcie0-refclk-gated {
53 compatible = "gpio-gate-clock";
54 clocks = <&pcie0_refclk>;
55 #clock-cells = <0>;
56 enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
57 };
58
59 reg_audio: regulator-audio {
60 compatible = "regulator-fixed";
61 regulator-name = "3v3_aud";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
65 enable-active-high;
66 };
67
68 reg_usbotg1: regulator-usbotg1 {
69 compatible = "regulator-fixed";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_reg_usb_otg1>;
72 regulator-name = "usb_otg_vbus";
73 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <5000000>;
75 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
76 enable-active-high;
77 };
78
79 reg_camera: regulator-camera {
80 compatible = "regulator-fixed";
81 regulator-name = "mipi_pwr";
82 regulator-min-microvolt = <2800000>;
83 regulator-max-microvolt = <2800000>;
84 gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
85 enable-active-high;
86 startup-delay-us = <100000>;
87 };
88
89 reg_pcie0: regulator-pcie {
90 compatible = "regulator-fixed";
91 regulator-name = "pci_pwr_en";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 enable-active-high;
95 gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
96 startup-delay-us = <100000>;
97 };
98
99 reg_usdhc2_vmmc: regulator-usdhc2 {
100 compatible = "regulator-fixed";
101 regulator-name = "VSD_3V3";
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
104 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
105 enable-active-high;
106 };
107
108 sound-dmic {
109 compatible = "simple-audio-card";
110 simple-audio-card,name = "dmic";
111 simple-audio-card,format = "pdm";
112 simple-audio-card,bitclock-master = <&dailink_master>;
113 simple-audio-card,frame-master = <&dailink_master>;
114
115 dailink_master: simple-audio-card,cpu {
116 sound-dai = <&micfil>;
117 };
118
119 simple-audio-card,codec {
120 sound-dai = <&dmic_codec>;
121 };
122 };
123
124 sound-wm8962 {
125 compatible = "simple-audio-card";
126 simple-audio-card,name = "wm8962";
127 simple-audio-card,format = "i2s";
128 simple-audio-card,widgets = "Headphone", "Headphones",
129 "Microphone", "Headset Mic",
130 "Speaker", "Speaker";
131 simple-audio-card,routing = "Headphones", "HPOUTL",
132 "Headphones", "HPOUTR",
133 "Speaker", "SPKOUTL",
134 "Speaker", "SPKOUTR",
135 "Headset Mic", "MICBIAS",
136 "IN3R", "Headset Mic";
137
138 simple-audio-card,cpu {
139 sound-dai = <&sai3>;
140 };
141
142 simple-audio-card,codec {
143 sound-dai = <&wm8962>;
144 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
145 frame-master;
146 bitclock-master;
147 };
148 };
149};
150
151&csi {
152 status = "okay";
153};
154
155&ecspi2 {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_espi2>;
158 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
159 status = "okay";
160
161 eeprom@0 {
162 compatible = "microchip,at25160bn", "atmel,at25";
163 reg = <0>;
164 spi-max-frequency = <5000000>;
165 spi-cpha;
166 spi-cpol;
167 pagesize = <32>;
168 size = <2048>;
169 address-width = <16>;
170 };
171};
172
173&i2c2 {
174 clock-frequency = <400000>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_i2c2>;
177 status = "okay";
178
179 camera@10 {
180 compatible = "ovti,ov5640";
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_ov5640>;
183 reg = <0x10>;
184 clocks = <&clk IMX8MM_CLK_CLKO1>;
185 clock-names = "xclk";
186 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
187 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
188 assigned-clock-rates = <24000000>;
189 AVDD-supply = <&reg_camera>; /* 2.8v */
190 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
191 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
192
193 port {
194 /* MIPI CSI-2 bus endpoint */
195 ov5640_to_mipi_csi2: endpoint {
196 remote-endpoint = <&imx8mm_mipi_csi_in>;
197 clock-lanes = <0>;
198 data-lanes = <1 2>;
199 };
200 };
201 };
202};
203
204&i2c4 {
205 clock-frequency = <400000>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_i2c4>;
208 status = "okay";
209
210 wm8962: audio-codec@1a {
211 compatible = "wlf,wm8962";
212 reg = <0x1a>;
213 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
214 DCVDD-supply = <&reg_audio>;
215 DBVDD-supply = <&reg_audio>;
216 AVDD-supply = <&reg_audio>;
217 CPVDD-supply = <&reg_audio>;
218 MICVDD-supply = <&reg_audio>;
219 PLLVDD-supply = <&reg_audio>;
220 SPKVDD1-supply = <&reg_audio>;
221 SPKVDD2-supply = <&reg_audio>;
222 gpio-cfg = <
223 0x0000 /* 0:Default */
224 0x0000 /* 1:Default */
225 0x0000 /* 2:FN_DMICCLK */
226 0x0000 /* 3:Default */
227 0x0000 /* 4:FN_DMICCDAT */
228 0x0000 /* 5:Default */
229 >;
230 #sound-dai-cells = <0>;
231 };
232
233 pca6416_0: gpio@20 {
234 compatible = "nxp,pcal6416";
235 reg = <0x20>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_pcal6414>;
238 gpio-controller;
239 #gpio-cells = <2>;
240 interrupt-parent = <&gpio4>;
241 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
242 };
243
244 pca6416_1: gpio@21 {
245 compatible = "nxp,pcal6416";
246 reg = <0x21>;
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-parent = <&gpio4>;
250 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
251 };
252};
253
254&micfil {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_pdm>;
257 assigned-clocks = <&clk IMX8MM_CLK_PDM>;
258 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
259 assigned-clock-rates = <49152000>;
260 status = "okay";
261};
262
263&mipi_csi {
264 status = "okay";
265 ports {
266 port@0 {
267 imx8mm_mipi_csi_in: endpoint {
268 remote-endpoint = <&ov5640_to_mipi_csi2>;
269 data-lanes = <1 2>;
270 };
271 };
272 };
273};
274
275&pcie_phy {
276 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
277 fsl,tx-deemph-gen1 = <0x2d>;
278 fsl,tx-deemph-gen2 = <0xf>;
279 fsl,clkreq-unsupported;
280 clocks = <&pcie0_refclk_gated>;
281 clock-names = "ref";
282 status = "okay";
283};
284
285&pcie0 {
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_pcie0>;
288 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
289 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
290 <&clk IMX8MM_CLK_PCIE1_AUX>;
291 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
292 <&clk IMX8MM_CLK_PCIE1_CTRL>;
293 assigned-clock-rates = <10000000>, <250000000>;
294 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
295 <&clk IMX8MM_SYS_PLL2_250M>;
296 vpcie-supply = <&reg_pcie0>;
297 status = "okay";
298};
299
300&sai3 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_sai3>;
303 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
304 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
305 assigned-clock-rates = <24576000>;
306 fsl,sai-mclk-direction-output;
307 status = "okay";
308};
309
310&snvs_pwrkey {
311 status = "okay";
312};
313
314&uart2 { /* console */
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_uart2>;
317 status = "okay";
318};
319
320&uart3 {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_uart3>;
323 assigned-clocks = <&clk IMX8MM_CLK_UART3>;
324 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
325 uart-has-rtscts;
326 status = "okay";
327};
328
329&usbotg1 {
330 vbus-supply = <&reg_usbotg1>;
331 disable-over-current;
332 dr_mode = "otg";
333 status = "okay";
334};
335
336&usbotg2 {
337 disable-over-current;
338 dr_mode = "host";
339 status = "okay";
340};
341
342&usbphynop2 {
343 reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
344};
345
346&usdhc2 {
347 pinctrl-names = "default", "state_100mhz", "state_200mhz";
348 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
349 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
350 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
351 bus-width = <4>;
352 vmmc-supply = <&reg_usdhc2_vmmc>;
353 status = "okay";
354};
355
356&iomuxc {
357 pinctrl_espi2: espi2grp {
358 fsl,pins = <
359 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
360 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
361 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
362 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x41
363 >;
364 };
365
366 pinctrl_i2c2: i2c2grp {
367 fsl,pins = <
368 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
369 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
370 >;
371 };
372
373 pinctrl_i2c4: i2c4grp {
374 fsl,pins = <
375 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
376 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
377 >;
378 };
379
380 pinctrl_led3: led3grp {
381 fsl,pins = <
382 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
383 >;
384 };
385
386 pinctrl_ov5640: ov5640grp {
387 fsl,pins = <
388 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
389 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
390 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
391 >;
392 };
393
394 pinctrl_pcal6414: pcal6414-gpiogrp {
395 fsl,pins = <
396 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
397 >;
398 };
399
400 pinctrl_pdm: pdmgrp {
401 fsl,pins = <
402 MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
403 MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
404 >;
405 };
406
407 pinctrl_reg_usb_otg1: usbotg1grp {
408 fsl,pins = <
409 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
410 >;
411 };
412
413 pinctrl_pcie0: pcie0grp {
414 fsl,pins = <
415 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
416 >;
417 };
418
419 pinctrl_sai3: sai3grp {
420 fsl,pins = <
421 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
422 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
423 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
424 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
425 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
426 >;
427 };
428
429 pinctrl_uart2: uart2grp {
430 fsl,pins = <
431 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
432 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
433 >;
434 };
435
436 pinctrl_uart3: uart3grp {
437 fsl,pins = <
438 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
439 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
440 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
441 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
442 >;
443 };
444
445 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
446 fsl,pins = <
447 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
448 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
449 >;
450 };
451
452 pinctrl_usdhc2: usdhc2grp {
453 fsl,pins = <
454 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
455 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
456 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
457 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
458 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
459 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
460 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
461 >;
462 };
463
464 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
465 fsl,pins = <
466 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
467 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
468 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
469 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
470 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
471 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
472 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
473 >;
474 };
475
476 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
477 fsl,pins = <
478 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
479 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
480 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
481 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
482 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
483 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
484 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
485 >;
486 };
487};