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git01.mediatek.com / filogic / uboot / dd15930c72301791084b9e257aaa805af02c92d9 / . / arch / arm / include / asm / arch-s3c24x0 / iomux.h
blob: cc22de749e26d3ea4ed04b24e166ad41b7646ced [file] [log] [blame]
Gabriel Huaudd159302012-05-02 10:49:55 +0000[diff] [blame^]1/*
2 * Copyright (c) 2012
3 *
4 * Gabriel Huau <contact@huau-gabriel.fr>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef _S3C24X0_IOMUX_H_
26#define _S3C24X0_IOMUX_H_
27
28enum s3c2440_iomux_func {
29 /* PORT A */
30 IOMUXA_ADDR0 = 1,
31 IOMUXA_ADDR16 = (1 << 1),
32 IOMUXA_ADDR17 = (1 << 2),
33 IOMUXA_ADDR18 = (1 << 3),
34 IOMUXA_ADDR19 = (1 << 4),
35 IOMUXA_ADDR20 = (1 << 5),
36 IOMUXA_ADDR21 = (1 << 6),
37 IOMUXA_ADDR22 = (1 << 7),
38 IOMUXA_ADDR23 = (1 << 8),
39 IOMUXA_ADDR24 = (1 << 9),
40 IOMUXA_ADDR25 = (1 << 10),
41 IOMUXA_ADDR26 = (1 << 11),
42 IOMUXA_nGCS1 = (1 << 12),
43 IOMUXA_nGCS2 = (1 << 13),
44 IOMUXA_nGCS3 = (1 << 14),
45 IOMUXA_nGCS4 = (1 << 15),
46 IOMUXA_nGCS5 = (1 << 16),
47 IOMUXA_CLE = (1 << 17),
48 IOMUXA_ALE = (1 << 18),
49 IOMUXA_nFWE = (1 << 19),
50 IOMUXA_nFRE = (1 << 20),
51 IOMUXA_nRSTOUT = (1 << 21),
52 IOMUXA_nFCE = (1 << 22),
53
54 /* PORT B */
55 IOMUXB_nXDREQ0 = (2 << 20),
56 IOMUXB_nXDACK0 = (2 << 18),
57 IOMUXB_nXDREQ1 = (2 << 16),
58 IOMUXB_nXDACK1 = (2 << 14),
59 IOMUXB_nXBREQ = (2 << 12),
60 IOMUXB_nXBACK = (2 << 10),
61 IOMUXB_TCLK0 = (2 << 8),
62 IOMUXB_TOUT3 = (2 << 6),
63 IOMUXB_TOUT2 = (2 << 4),
64 IOMUXB_TOUT1 = (2 << 2),
65 IOMUXB_TOUT0 = 2,
66
67 /* PORT C */
68 IOMUXC_VS7 = (2 << 30),
69 IOMUXC_VS6 = (2 << 28),
70 IOMUXC_VS5 = (2 << 26),
71 IOMUXC_VS4 = (2 << 24),
72 IOMUXC_VS3 = (2 << 22),
73 IOMUXC_VS2 = (2 << 20),
74 IOMUXC_VS1 = (2 << 18),
75 IOMUXC_VS0 = (2 << 16),
76 IOMUXC_LCD_LPCREVB = (2 << 14),
77 IOMUXC_LCD_LPCREV = (2 << 12),
78 IOMUXC_LCD_LPCOE = (2 << 10),
79 IOMUXC_VM = (2 << 8),
80 IOMUXC_VFRAME = (2 << 6),
81 IOMUXC_VLINE = (2 << 4),
82 IOMUXC_VCLK = (2 << 2),
83 IOMUXC_LEND = 2,
84 IOMUXC_I2SSDI = (3 << 8),
85
86 /* PORT D */
87 IOMUXD_VS23 = (2 << 30),
88 IOMUXD_VS22 = (2 << 28),
89 IOMUXD_VS21 = (2 << 26),
90 IOMUXD_VS20 = (2 << 24),
91 IOMUXD_VS19 = (2 << 22),
92 IOMUXD_VS18 = (2 << 20),
93 IOMUXD_VS17 = (2 << 18),
94 IOMUXD_VS16 = (2 << 16),
95 IOMUXD_VS15 = (2 << 14),
96 IOMUXD_VS14 = (2 << 12),
97 IOMUXD_VS13 = (2 << 10),
98 IOMUXD_VS12 = (2 << 8),
99 IOMUXD_VS11 = (2 << 6),
100 IOMUXD_VS10 = (2 << 4),
101 IOMUXD_VS9 = (2 << 2),
102 IOMUXD_VS8 = 2,
103 IOMUXD_nSS0 = (3 << 30),
104 IOMUXD_nSS1 = (3 << 28),
105 IOMUXD_SPICLK1 = (3 << 20),
106 IOMUXD_SPIMOSI1 = (3 << 18),
107 IOMUXD_SPIMISO1 = (3 << 16),
108
109 /* PORT E */
110 IOMUXE_IICSDA = (2 << 30),
111 IOMUXE_IICSCL = (2 << 28),
112 IOMUXE_SPICLK0 = (2 << 26),
113 IOMUXE_SPIMOSI0 = (2 << 24),
114 IOMUXE_SPIMISO0 = (2 << 22),
115 IOMUXE_SDDAT3 = (2 << 20),
116 IOMUXE_SDDAT2 = (2 << 18),
117 IOMUXE_SDDAT1 = (2 << 16),
118 IOMUXE_SDDAT0 = (2 << 14),
119 IOMUXE_SDCMD = (2 << 12),
120 IOMUXE_SDCLK = (2 << 10),
121 IOMUXE_I2SDO = (2 << 8),
122 IOMUXE_I2SDI = (2 << 6),
123 IOMUXE_CDCLK = (2 << 4),
124 IOMUXE_I2SSCLK = (2 << 2),
125 IOMUXE_I2SLRCK = 2,
126 IOMUXE_AC_SDATA_OUT = (3 << 8),
127 IOMUXE_AC_SDATA_IN = (3 << 6),
128 IOMUXE_AC_nRESET = (3 << 4),
129 IOMUXE_AC_BIT_CLK = (3 << 2),
130 IOMUXE_AC_SYNC = 3,
131
132 /* PORT F */
133 IOMUXF_EINT7 = (2 << 14),
134 IOMUXF_EINT6 = (2 << 12),
135 IOMUXF_EINT5 = (2 << 10),
136 IOMUXF_EINT4 = (2 << 8),
137 IOMUXF_EINT3 = (2 << 6),
138 IOMUXF_EINT2 = (2 << 4),
139 IOMUXF_EINT1 = (2 << 2),
140 IOMUXF_EINT0 = 2,
141
142 /* PORT G */
143 IOMUXG_EINT23 = (2 << 30),
144 IOMUXG_EINT22 = (2 << 28),
145 IOMUXG_EINT21 = (2 << 26),
146 IOMUXG_EINT20 = (2 << 24),
147 IOMUXG_EINT19 = (2 << 22),
148 IOMUXG_EINT18 = (2 << 20),
149 IOMUXG_EINT17 = (2 << 18),
150 IOMUXG_EINT16 = (2 << 16),
151 IOMUXG_EINT15 = (2 << 14),
152 IOMUXG_EINT14 = (2 << 12),
153 IOMUXG_EINT13 = (2 << 10),
154 IOMUXG_EINT12 = (2 << 8),
155 IOMUXG_EINT11 = (2 << 6),
156 IOMUXG_EINT10 = (2 << 4),
157 IOMUXG_EINT9 = (2 << 2),
158 IOMUXG_EINT8 = 2,
159 IOMUXG_TCLK1 = (3 << 22),
160 IOMUXG_nCTS1 = (3 << 20),
161 IOMUXG_nRTS1 = (3 << 18),
162 IOMUXG_SPICLK1 = (3 << 14),
163 IOMUXG_SPIMOSI1 = (3 << 12),
164 IOMUXG_SPIMISO1 = (3 << 10),
165 IOMUXG_LCD_PWRDN = (3 << 8),
166 IOMUXG_nSS1 = (3 << 6),
167 IOMUXG_nSS0 = (3 << 4),
168
169 /* PORT H */
170 IOMUXH_CLKOUT1 = (2 << 20),
171 IOMUXH_CLKOUT0 = (2 << 18),
172 IOMUXH_UEXTCLK = (2 << 16),
173 IOMUXH_RXD2 = (2 << 14),
174 IOMUXH_TXD2 = (2 << 12),
175 IOMUXH_RXD1 = (2 << 10),
176 IOMUXH_TXD1 = (2 << 8),
177 IOMUXH_RXD0 = (2 << 6),
178 IOMUXH_TXD0 = (2 << 4),
179 IOMUXH_nRTS0 = (2 << 2),
180 IOMUXH_nCTS0 = 2,
181 IOMUXH_nCTS1 = (3 << 14),
182 IOMUXH_nRTS1 = (3 << 12),
183
184 /* PORT J */
185 IOMUXJ_CAMRESET = (2 << 24),
186 IOMUXJ_CAMCLKOUT = (2 << 22),
187 IOMUXJ_CAMHREF = (2 << 20),
188 IOMUXJ_CAMVSYNC = (2 << 18),
189 IOMUXJ_CAMPCLK = (2 << 16),
190 IOMUXJ_CAMDATA7 = (2 << 14),
191 IOMUXJ_CAMDATA6 = (2 << 12),
192 IOMUXJ_CAMDATA5 = (2 << 10),
193 IOMUXJ_CAMDATA4 = (2 << 8),
194 IOMUXJ_CAMDATA3 = (2 << 6),
195 IOMUXJ_CAMDATA2 = (2 << 4),
196 IOMUXJ_CAMDATA1 = (2 << 2),
197 IOMUXJ_CAMDATA0 = 2
198};
199
200#endif